`make sim-rtl` fails due to redeclaration of modules about chipyard HOT 3 CLOSED

Yea that makes sense. I will make the change in sram_compiler.
The same issue also exists for the standard cell library. The Decap cells (*OD*DCAP*) have the same names across different Vt flavors. The plan is to shred them from the lvt and hvt files.

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Fix for this: add -error=noMPD option in vcs to suppress the error.
Not sure if this is a good long term solution.

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-top was removed to remove a different VCS error, one which essentially said that two different designs were declared as the top.

You can add back sim.inputs.tb_name to the sim.mk so that it appears in sim-inputs.yml. If you specify -error=noMPD, I presume it just ignores redeclarations and assumes the last one is valid - this would work but could hide some problems later, so it's not good long-term.

Anyways, I think I see the root issue - it's that the SS and FF corners have different Verilog files (I presume this is the output of the TSMC memory compiler). I did a comparison of the two and they're only different by some timing params, which is expected. For RTL sim, these params don't get used; for gate-level timing-annotated sim, you would only want to use the file corresponding to the corner you want to check against. TL;DR, only 1 memory Verilog file should be used for simulation - perhaps you can modify the plugin's sram_compiler tool for now to only include the TT corner Verilog?

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