MMIO and front bus port not generated in MMIOScratchpadOnlyRocketConfig about chipyard HOT 9 CLOSED

module ChipTop(                                                                                                      
  input         serial_tl_bits_in_valid,                                                                             
  input  [31:0] serial_tl_bits_in_bits,                                                                              
  input         serial_tl_bits_out_ready,                                                                            
                axi4_mmio_0_bits_aw_ready,                                                                           
                axi4_mmio_0_bits_w_ready,                                                                            
                axi4_mmio_0_bits_b_valid,                                                                            
  input  [3:0]  axi4_mmio_0_bits_b_bits_id,                                                                          
  input  [1:0]  axi4_mmio_0_bits_b_bits_resp,                                                                        
  input         axi4_mmio_0_bits_ar_ready,                                                                           
                axi4_mmio_0_bits_r_valid,                                                                            
  input  [3:0]  axi4_mmio_0_bits_r_bits_id,                                                                          
  input  [63:0] axi4_mmio_0_bits_r_bits_data,                                                                        
  input  [1:0]  axi4_mmio_0_bits_r_bits_resp,                                                                        
  input         axi4_mmio_0_bits_r_bits_last,                                                                        
                custom_boot,                                                                                         
                clock_clock,                                                                                         
                reset,                                                                                               
                jtag_TCK,                                                                                            
                jtag_TMS,                                                                                            
                jtag_TDI,                                                                                            
                uart_0_rxd,                                                                                          
  output        serial_tl_clock,                                                                                     
                serial_tl_bits_in_ready,                                                                             
                serial_tl_bits_out_valid,                                                                            
  output [31:0] serial_tl_bits_out_bits,                                                                             
  output        axi4_mmio_0_clock,                                                                                   
                axi4_mmio_0_reset,                                                                                   
                axi4_mmio_0_bits_aw_valid,                                                                           
  output [3:0]  axi4_mmio_0_bits_aw_bits_id,                                                                         
  output [30:0] axi4_mmio_0_bits_aw_bits_addr,                                                                       
  output [7:0]  axi4_mmio_0_bits_aw_bits_len,                                                                        
  output [2:0]  axi4_mmio_0_bits_aw_bits_size,                                                                       
  output [1:0]  axi4_mmio_0_bits_aw_bits_burst,                                                                      
  output        axi4_mmio_0_bits_aw_bits_lock,                                                                       
  output [3:0]  axi4_mmio_0_bits_aw_bits_cache,                                                                        output [2:0]  axi4_mmio_0_bits_aw_bits_prot,                                                                         output [3:0]  axi4_mmio_0_bits_aw_bits_qos,                                                                          output        axi4_mmio_0_bits_w_valid,                                                                              output [63:0] axi4_mmio_0_bits_w_bits_data,                                                                          output [7:0]  axi4_mmio_0_bits_w_bits_strb,                                                                          output        axi4_mmio_0_bits_w_bits_last,                                                                                        axi4_mmio_0_bits_b_ready,                                                                                            axi4_mmio_0_bits_ar_valid,                                                                             output [3:0]  axi4_mmio_0_bits_ar_bits_id,                                                                           output [30:0] axi4_mmio_0_bits_ar_bits_addr,                                                                         output [7:0]  axi4_mmio_0_bits_ar_bits_len,                                                                        
  output [2:0]  axi4_mmio_0_bits_ar_bits_size,                                                                       
  output [1:0]  axi4_mmio_0_bits_ar_bits_burst,                                                                      
  output        axi4_mmio_0_bits_ar_bits_lock,                                                                       
  output [3:0]  axi4_mmio_0_bits_ar_bits_cache,
  output [2:0]  axi4_mmio_0_bits_ar_bits_prot,
  output [3:0]  axi4_mmio_0_bits_ar_bits_qos,
  output        axi4_mmio_0_bits_r_ready,
                jtag_TDO,
                uart_0_txd
);