Topic: digitaldesign Goto Github
Some thing interesting about digitaldesign
Some thing interesting about digitaldesign
digitaldesign,Full AES (Verilog)
User: abdelrahman-adel610
Home Page: https://www.geeksforgeeks.org/advanced-encryption-standard-aes
digitaldesign,A repo to store the coursework I do in college! 🎓
User: abxhr
digitaldesign,Digital Design Timing Constraints
User: ahagmann
digitaldesign,This repository contains scripts that I create through my digital design course in Verilog, VHDL, SystemVerilog etc..
User: ahegazy
digitaldesign,EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
User: ahmed-agiza
Home Page: https://edaviewer.com
digitaldesign,Educational repo for storing my practice sessions with digital systems as well as solutions to online courses or university courses I take. These implementations are done in VHDL or Verilog.
User: antencarnacion
digitaldesign,Took a module on Digital Design Fundamentals during my year 2 of my undergraduate studies of Electronic Circuits done using VHDL and Verilog, with a final project on FPGA Programmed Flappy Bird Gaming System using Sound and Light effects.
User: anuragschatterjee
digitaldesign,This repository contains a few useful Verilog modules
User: arna-maity
digitaldesign,For all the fidget spinneteers out there
User: darter-funny
digitaldesign,Школа инженера от DigitalDesign
User: escaper2
Home Page: https://digdes.ru/it-university/shkola-inzhenera
digitaldesign,This repository contains different modules which execute arithmetic operations.
User: gabbedt
digitaldesign,FIFO buffer library. Written and verified in SystemVerilog. Can be synthetised in ASIC or FPGA.
User: gabbedt
digitaldesign,Computer Organization and Digital Design Projects - CS1050 - Semester 2
User: irash-perera
digitaldesign,Miscellaneous stuff from the NDSU Digital Design Class
User: jacobhuesman
digitaldesign,a quick interface to any digital device that features magazines as a product
User: marconip
digitaldesign,VHDL tutorial
User: mohamedsalem80
Home Page: https://drive.google.com/drive/folders/19KyYJOgZSFlZfGzc6FWgkRxtoCVd9kQp
digitaldesign,RTL Designs along with testbenches to verify them written in Verilog. Icarus Verilog an open source simulator was used for simulations.
User: mshetty149
digitaldesign,Placer and Router for standard cells
User: mshetty149
digitaldesign,Basic digital lock system for safes, employing logic gates 🔐
User: myriam2002
digitaldesign, CipherX is a verification project for Advanced Encryption Standard (AES-128) using Universal Verification Methodology (UVM). It leverages Verilog, SystemVerilog, and Python to ensure robust encryption algorithm validation, integrating comprehensive UVM components and tests.
User: pirate-emperor
digitaldesign,Repository containing the code for implementing the classic game Pong on a Nexys A7 Digilent FPGA development board.
User: rhit-bryantlj
digitaldesign,IP Module For LTC2311 ADC
User: serhaturtis
digitaldesign,4 bit divider design using first divider algorithm
User: sidhantp1906
digitaldesign,PWM module using verilig HDL in XILINX ISE
User: sidhantp1906
digitaldesign,Very simple Cortex-M1 SoC design based on ARM DesignStart
User: siorpaes
digitaldesign,5 stage pipelined RISC-V core with AXI3 bus protocol between the directly mapped cache and main memory.
User: tharunchitipolu
digitaldesign,RTL Design and Synthesis Workshop using Verilog with Sky130 Technology
User: vishakha7501
digitaldesign,images equalizer in VHDL
User: vladmariancimpeanu
digitaldesign,VHDL controller for dynamic protocol switching (CAN, LIN, FlexRay).
User: yezzfusl
digitaldesign,A slot machine created in System Verilog. It was built, simulated, synthesized, and implemented in Vivado, for use on the Xilinx Basys 3 board.
User: z4chh
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