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OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Home Page: https://theopenroadproject.org/

License: BSD 3-Clause "New" or "Revised" License

CMake 0.25% Shell 0.07% C++ 21.72% Tcl 2.32% Verilog 72.97% SWIG 0.46% Python 0.51% C 0.82% Dockerfile 0.01% Yacc 0.63% Ruby 0.01% Cuda 0.01% Roff 0.23% Nix 0.01%
opendb-database openroad lef verilog timing-analysis def eda rtl gdsii cpp

openroad's Introduction

OpenROAD

Build Status Coverity Scan Status Documentation Status CII Best Practices

About OpenROAD

OpenROAD is the leading open-source, foundational application for semiconductor digital design. The OpenROAD flow delivers an Autonomous, No-Human-In-Loop (NHIL) flow, 24 hour turnaround from RTL-GDSII for rapid design exploration and physical design implementation.

%%{
  init: {
    'theme': 'neutral',
    'themeVariables': {
      'textColor': '#000000',
      'noteTextColor' : '#000000',
      'fontSize': '20px'
    }
  }
}%%

flowchart LR
    b0[                  ] --- b2[ ] --- b4[ ] --- ORFlow --- b1[ ] --- b3[ ] --- b5[                  ]
    style b0 stroke-width:0px, fill: #FFFFFF00, color:#FFFFFF00
    style b1 stroke-width:0px, fill: #FFFFFF00
    style b2 stroke-width:0px, fill: #FFFFFF00
    style b3 stroke-width:0px, fill: #FFFFFF00
    style b4 stroke-width:0px, fill: #FFFFFF00
    style b5 stroke-width:0px, fill: #FFFFFF00, color:#FFFFFF00

    linkStyle 0 stroke-width:0px
    linkStyle 1 stroke-width:0px
    linkStyle 2 stroke-width:0px
    linkStyle 3 stroke-width:0px
    linkStyle 4 stroke-width:0px
    linkStyle 5 stroke-width:0px


    subgraph ORFlow
    direction TB
    style ORFlow fill:#ffffff00, stroke-width:0px
        A[Verilog\n+ libraries\n + constraints] --> FLOW
        style A fill:#74c2b5,stroke:#000000,stroke-width:4px
        subgraph FLOW
        style FLOW fill:#FFFFFF00,stroke-width:4px

        direction TB
            B[Synthesis]
            B --> C[Floorplan]
            C --> D[Placement]
            D --> E[Clock Tree Synthesis]
            E --> F[Routing]
            F --> G[Finishing]
            style B fill:#f8cecc,stroke:#000000,stroke-width:4px
            style C fill:#fff2cc,stroke:#000000,stroke-width:4px
            style D fill:#cce5ff,stroke:#000000,stroke-width:4px
            style E fill:#67ab9f,stroke:#000000,stroke-width:4px
            style F fill:#fa6800,stroke:#000000,stroke-width:4px
            style G fill:#ff6666,stroke:#000000,stroke-width:4px
        end

        FLOW --> H[GDSII\n Final Layout]
        %% H --- H1[ ]
        %% style H1 stroke-width:0px, fill: #FFFFFF00
        %% linkStyle 11 stroke-width:0px
        style H fill:#ff0000,stroke:#000000,stroke-width:4px
    end

OpenROAD Mission

OpenROAD eliminates the barriers of cost, schedule risk and uncertainty in hardware design to promote open access to rapid, low-cost IC design software and expertise and system innovation. The OpenROAD application enables flexible flow control through an API with bindings in Tcl and Python.

OpenROAD is used in research and commercial applications such as,

OpenROAD fosters a vibrant ecosystem of users through active collaboration and partnership through software development and key alliances. Our growing user community includes hardware designers, software engineers, industry collaborators, VLSI enthusiasts, students and researchers.

OpenROAD strongly advocates and enables IC design-based education and workforce development initiatives through training content and courses across several global universities, the Google-SkyWater shuttles also includes GlobalFoundries shuttles, design contests and IC design workshops. The OpenROAD flow has been successfully used to date in over 600 silicon-ready tapeouts for technologies up to 12nm.

Getting Started with OpenROAD-flow-scripts

OpenROAD provides OpenROAD-flow-scripts as a native, ready-to-use prototyping and tapeout flow. However, it also enables the creation of any custom flow controllers based on the underlying tools, database and analysis engines. Please refer to the flow documentation here.

OpenROAD-flow-scripts (ORFS) is a fully autonomous, RTL-GDSII flow for rapid architecture and design space exploration, early prediction of QoR and detailed physical design implementation. However, ORFS also enables manual intervention for finer user control of individual flow stages through Tcl commands and Python APIs.

Figure below shows the main stages of the OpenROAD-flow-scripts:

%%{init: { 'logLevel': 'debug', 'theme': 'dark'
  } }%%
timeline
  title RTL-GDSII Using OpenROAD-flow-scripts
  Synthesis
    : Inputs  [RTL, SDC, .lib, .lef]
    : Logic Synthesis  (Yosys)
    : Output files  [Netlist, SDC]
  Floorplan
    : Floorplan Initialization
    : IO placement  (random)
    : Timing-driven mixed-size placement
    : Macro placement
    : Tapcell and welltie insertion
    : PDN generation
  Placement
    : Global placement without placed IOs
    : IO placement  (optimized)
    : Global placement with placed IOs
    : Resizing and buffering
    : Detailed placement
  CTS : Clock Tree Synthesis
    : Timing optimization
    : Filler cell insertion
  Routing
    : Global Routing
    : Detailed Routing
  Finishing
    : Metal Fill insertion
    : Signoff timing report
    : Generate GDSII  (KLayout)
    : DRC/LVS check (KLayout)

Here are the main steps for a physical design implementation using OpenROAD;

  • Floorplanning
    • Floorplan initialization - define the chip area, utilization
    • IO pin placement (for designs without pads)
    • Tap cell and well tie insertion
    • PDN- power distribution network creation
  • Global Placement
    • Macro placement (RAMs, embedded macros)
    • Standard cell placement
    • Automatic placement optimization and repair for max slew, max capacitance, and max fanout violations and long wires
  • Detailed Placement
    • Legalize placement - align to grid, adhere to design rules
    • Incremental timing analysis for early estimates
  • Clock Tree Synthesis
    • Insert buffers and resize for high fanout nets
  • Optimize setup/hold timing
  • Global Routing
    • Antenna repair
    • Create routing guides
  • Detailed Routing
    • Legalize routes, DRC-correct routing to meet timing, power constraints
  • Chip Finishing
    • Parasitic extraction using OpenRCX
    • Final timing verification
    • Final physical verification
    • Dummy metal fill for manufacturability
    • Use KLayout or Magic using generated GDS for DRC signoff

GUI

The OpenROAD GUI is a powerful visualization, analysis, and debugging tool with a customizable Tcl interface. The below figures show GUI views for various flow stages including floorplanning, placement congestion, CTS and post-routed design.

Floorplan

ibex_floorplan.webp

Automatic Hierarchical Macro Placement

Ariane133

Placement Congestion Visualization

pl_congestion.webp

CTS

clk_routing.webp

Routing

ibex_routing.webp

PDK Support

The OpenROAD application is PDK independent. However, it has been tested and validated with specific PDKs in the context of various flow controllers.

OpenLane supports SkyWater 130nm and GlobalFoundries 180nm.

OpenROAD-flow-scripts supports several public and private PDKs including:

Open-Source PDKs

  • GF180 - 180nm
  • SKY130 - 130nm
  • Nangate45 - 45nm
  • ASAP7 - Predictive FinFET 7nm

Proprietary PDKs

These PDKS are supported in OpenROAD-flow-scripts only. They are used to test and calibrate OpenROAD against commercial platforms and ensure good QoR. The PDKs and platform-specific files for these kits cannot be provided due to NDA restrictions. However, if you are able to access these platforms independently, you can create the necessary platform-specific files yourself.

  • GF55 - 55nm
  • GF12 - 12nm
  • Intel22 - 22nm
  • Intel16 - 16nm
  • TSMC65 - 65nm

Tapeouts

OpenROAD has been used for full physical implementation in over 600 tapeouts in SKY130 and GF180 through the Google-sponsored, Efabless MPW shuttle and ChipIgnite programs.

shuttle.webp

OpenTitan SoC on GF12LP - Physical design and optimization using OpenROAD

OpenTitan_SoC.webp

Continuous Tapeout Integration into CI

The OpenROAD project actively adds successfully taped out MPW shuttle designs to the CI regression testing. Examples of designs include Open processor cores, RISC-V based SoCs, cryptocurrency miners, robotic app processors, amateur satellite radio transceivers, OpenPower-based Microwatt etc.

Build OpenROAD

To build OpenROAD tools locally in your machine, follow steps from here.

Regression Tests

There are a set of executable regression test scripts in ./test/.

# run tests for all tools
./test/regression

# run all flow tests
./test/regression flow

# run <tool> tests
./test/regression <tool>

# run all <tool>-specific unit tests
cd src/<tool>
./test/regression

# run only <TEST_NAME> for <tool>
cd src/<tool>
./test/regression <TEST_NAME>

The flow tests check results such as worst slack against reference values. Use report_flow_metrics [test]... to see all of the metrics.

% report_flow_metrics gcd_nangate45
                       insts    area util slack_min slack_max  tns_max clk_skew max_slew max_cap max_fanout DPL ANT drv
gcd_nangate45            368     564  8.8     0.112    -0.015     -0.1    0.004        0       0          0   0   0   0

To update a failing regression, follow the instructions below:

# update log files (i.e. *ok)
save_ok <TEST_NAME>

# update "*.metrics" for tests that use flow test
save_flow_metrics <TEST_NAME> 

# update "*.metrics_limits" files
save_flow_metrics_limits <TEST_NAME>

Run

openroad [-help] [-version] [-no_init] [-exit] [-gui]
         [-threads count|max] [-log file_name] cmd_file
  -help              show help and exit
  -version           show version and exit
  -no_init           do not read .openroad init file
  -threads count|max use count threads
  -no_splash         do not show the license splash at startup
  -exit              exit after reading cmd_file
  -gui               start in gui mode
  -python            start with python interpreter [limited to db operations]
  -log <file_name>   write a log in <file_name>
  cmd_file           source cmd_file

OpenROAD sources the Tcl command file ~/.openroad unless the command line option -no_init is specified.

OpenROAD then sources the command file cmd_file if it is specified on the command line. Unless the -exit command line flag is specified, it enters an interactive Tcl command interpreter.

A list of the available tools/modules included in the OpenROAD app and their descriptions are available here.

Git Quickstart

OpenROAD uses Git for version control and contributions. Get familiarised with a quickstart tutorial to contribution here.

Understanding Warning and Error Messages

Seeing OpenROAD warnings or errors you do not understand? We have compiled a table of all messages and you may potentially find your answer here.

License

BSD 3-Clause License. See LICENSE file.

openroad's People

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openroad's Issues

opendp overlapping cells

Hello,
Opendp places cells over tapcells in the middle of the floorplan. It seems that providing the same input parameters (def and lef) to opendp that a legacy version of opendp doesn't produce the same wrong behavior (specifically this version https://github.com/sanggido/OpenDP).
Thank you

support for tclreadline (or equivalent) ?

Hi,

Not really an issue but it seems that I can't access command history through the up/down arrows. My regular tclsh/wish shells have access to it through a specific ~/.tclshrc file but apparently the build-in tcl shell does not use it. Maybe there is an alternate solution available or my build of OpenRoad is not supporting it because of some missign configuration ?

hv_inflation_ratio always 0,0

Hey (it's me again),
I'm able to run both DAC2012 bookshelf format (on 1.0.0) and ISPD2018 (on 1.1.0) with the routability option enabled and in order to verify it was working I was looking for a print that was non-zero for hv_inflation_ratio but all I see is 0, 0 for all the prints. Am I missing something? I want to play with the max_inflation_ratio parameter to see how results change, but I don't know how to confirm that this argument is taking effect.
Thanks!
ArEsKay3

auto_place_pins multiple layers

Hello,
auto_place_pins pin_layer Places pins on a single layer. It should be able to place vertical pins (sides of the die) and horizontal pins (top and bottom of the die) in separate layers.

Create a RPC interface as an optional replacement to tcl

Currently, if user wanna interact with OpenROAD, the only way is to invoke a tcl shell to send command and receive command. The result is hard to parse, and string only without type struct informations.
So I wonder if possible to add a json/protobuf based RPC interface as a optional replacement to tcl which contains a more serializable API for other program to interact with OpenROAD.

read_lef history.tcl error

Testing main branch build of openroad with test/gcd_flow1.tcl.
(other than that, got through def)

% read_lef NangateOpenCellLibrary.lef
Error: history.tcl, 330 invoked "return" outside of a proc.
Notice 0: Reading LEF file: NangateOpenCellLibrary.lef
Notice 0: Created 22 technology layers
Notice 0: Created 27 technology vias
Notice 0: Created 134 library cells
Notice 0: Finished LEF file: NangateOpenCellLibrary.lef

Error in README.md - # Write the db for future runs. write_db reg1.def

This is an error in the README.md file
The original reg1.def WILL BE overwritten when issuing the write_db reg1.def command ?
Should it not be

write_db reg1.db 

Also just spotted typo incorrect spelling is used - technogy in snippet below:

The read_lef and read_def commands can be used to build an OpenDB database as shown below. The read_lef -tech flag reads the technology portion of a LEF file. The read_lef -library flag reads the MACROs in the LEF file. If neither of the -tech and -library flags are specified they default to -tech -library if no technology has been read and -library if a technogy exists in the database.

read_lef liberty1.lef
read_def reg1.def
# Write the db for future runs.
write_db reg1.def

The read_verilog command is used to build an OpenDB database as shown below. Multiple verilog files for a hierarchical design can be read. The link_design command is used to flatten the design and make a database.

read_lef liberty1.lef
read_verilog reg1.v
link_design top
# Write the db for future runs.
write_db reg1.db

make[3]: don't know how to make /usr/ports/cad/replace/work/RePlAce-1.1.1-277-gcf289bb/src/replace/src/replace.i. Stop

You have

set(REPLACE_HOME ${PROJECT_SOURCE_DIR}/src/replace )
...
add_custom_command(OUTPUT ${REPLACE_WRAP}
  COMMAND ${SWIG_EXECUTABLE} -tcl8 -c++ -o ${REPLACE_WRAP} ${REPLACE_HOME}/src/replace.i
  WORKING_DIRECTORY ${REPLACE_HOME}
  DEPENDS ${REPLACE_HOME}/src/replace.i ${REPLACE_HOME}/include/replace/Replace.h
)

which looks for replace.i in ${PROJECT_SOURCE_DIR}/src/replace/src/replace.i which doesn't exist.

1.1.1-277-gcf289bb

Build fails:no matching member function for call to 'draw_text'

clang-8 fails:

/usr/ports/cad/replace/work/RePlAce-1.1.1-34-g253e2d3/src/plot.cpp:505:7: error: no matching member function for call to 'draw_text'
  img.draw_text(50, 50, imgName.c_str(), black, NULL, 1, 100);
  ~~~~^~~~~~~~~
/usr/ports/cad/replace/work/RePlAce-1.1.1-34-g253e2d3/module/CImg/CImg.h:44634:14: note: candidate function template not viable: no known conversion from 'nullptr_t' to 'const int' for 5th argument
    CImg<T>& draw_text(const int x0, const int y0,
             ^
/usr/ports/cad/replace/work/RePlAce-1.1.1-34-g253e2d3/module/CImg/CImg.h:44563:14: note: candidate template ignored: could not match 'const tc2 *' against 'nullptr_t'
    CImg<T>& draw_text(const int x0, const int y0,
             ^
/usr/ports/cad/replace/work/RePlAce-1.1.1-34-g253e2d3/module/CImg/CImg.h:44579:14: note: candidate template ignored: could not match 'CImgList<type-parameter-0-1>' against 'int'
    CImg<T>& draw_text(const int x0, const int y0,
             ^
/usr/ports/cad/replace/work/RePlAce-1.1.1-34-g253e2d3/module/CImg/CImg.h:44595:14: note: candidate template ignored: could not match 'const tc *' against 'nullptr_t'
    CImg<T>& draw_text(const int x0, const int y0,
             ^

See a full log with some other errors: https://people.freebsd.org/~yuri/replace.log

read_def does not support engineering notation for dimensions

I'm on site for the integration exercise and investigating using the router in a mixed flow with a third-party placer. The placer uses engineering notation (e.g. 1.89e+06 for 1890000) in all the geometry dimensions, and this is causing syntax errors in openroad. If I replace these with the numeric notation, it reads in successfully.

test.def:

VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN test ;
UNITS DISTANCE MICRONS 1000 ;

DIEAREA ( 0 0 ) ( 1.89e+06 1.5e+06 ) ;

END DESIGN

test2.def:

VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN test2 ;
UNITS DISTANCE MICRONS 1000 ;

DIEAREA ( 0 0 ) ( 1890000 1500000 ) ;

END DESIGN

Example:

% read_def test.def
Notice 0: 
Reading DEF file: test.def
Notice 0: Design: test
Notice 0: error: DEF:7: syntax error, reading 1.89e+06
% read_def test2.def
Notice 0: 
Reading DEF file: test2.def
Notice 0: Design: test2
Notice 0: Finished DEF file: test2.def

[pdngen] stripes not exposed as pins for LVS and power routing

Hello,

This is a feature needed for two main necessary purposes: LVS (to verify that all macros are powered) and power routing (power pins need to be exposed when a LEF is generated from the final routed DEF to be used in bigger designs).

Currently, both of these steps require manual intervention. Creating 2 0-area pins on top of a VDD and VSS stripes for the purpose of LVS does the job. Power routing is done entirely by hand (let me know if you need further details on this).

To eliminate these, in my opinion, (at least two) stripes should be exposed as power pins or perhaps extended to the macro boundary. Power routing could either (perhaps) be implemented as a special feature from FastRoute+TritonRoute (by specifying the required widths and metal layers) or through a new independent tool.

Let me know if you need further details,
Thanks

Build problems on Ubuntu 18.04

Hi I get a couple of problems when trying to build on Ubuntu 18.04

On Ubuntu, the TCL headers are in /usr/include/tcl/tcl.h, and compilations claim they can't find tcl.h. Which is odd, because the output of CMAKE seems to imply that it has found it correctly.

Also during a link step, involving pthreads, there was a complaint about a missing DSO file.

Keep up the good work!

Floorplanning - tracks origin(offset)

Hello,

Currently, the floorplanner produces the same set of tracks regardless of the die area definition based on the tracks file. This causes issues with unconventional definitions of the die area (e.g., not starting at ( 0 0 )). (see this).

Aren't the tracks supposed to follow the die area origin instead of assuming it starts at 0,0? Or were such cases intended to be handled by the tracks file; for example, by manually adding the required shifts there.

Thanks.

Improve error message when design doesn't fit

I believe the error message below is simply because there's no way this placement of the RAMs is going to work.

Can the error message be improved for the user?

[ERROR] RePlAce divergence detected. 
        Please decrease max_phi_cof value (REPL-4)

2_floorplan.def:

image

Failed git clone

I tried today to do a git clone of the repo according to the instructions, but part way through I got the error:

error: Server does not allow request for unadvertised object 10e8a5378637808ddaa1c313158e39d587c9bc38
Fetched in submodule path 'src/opendp', but it did not contain 10e8a5378637808ddaa1c313158e39d587c9bc38. Direct fetching of that commit failed.

Any ideas?

Segfaults in the MuxTest*.v series of tests

Check out the latest alpha-release master and run:

#  make DESIGN_CONFIG=`pwd`/designs/tiny-tests.mk DESIGN_NAME=MuxTest_width_1_inputs_1_outputs_1_pipeline_0
[deleted]
INFO: Total 0 worst path!
/bin/bash: line 17:  2214 Segmentation fault      (core dumped) RePlAce -bmflag etc -lef ./objects/nangate45/MuxTest_width_1_inputs_1_outputs_1_pipeline_0/merged_padded.lef -def ./results/nangate45/MuxTest_width_1_inputs_1_outputs_1_pipeline_0/2_floorplan.def -verilog ./results/nangate45/MuxTest_width_1_inputs_1_outputs_1_pipeline_0/2_floorplan.v -lib ./platforms/nangate45/NangateOpenCellLibrary_typical.lib -sdc ./results/nangate45/MuxTest_width_1_inputs_1_outputs_1_pipeline_0/2_floorplan.sdc -output ./results/nangate45/MuxTest_width_1_inputs_1_outputs_1_pipeline_0/replace -t 1 -timing -resPerMicron 1.59 -capPerMicron 0.235146e-12 -skipIP -plot -experi output -den 0.509 -initCoef 0.00002 -onlyGP 2>&1
      2215 Done                    | tee ./logs/nangate45/MuxTest_width_1_inputs_1_outputs_1_pipeline_0/3_1_RePlAce.log

Metal1 assumptions on macro placement

Hello,

Why is it assumed that block macros are supposed to have metal1 OBS? (i.e., the size of a macro seems to be calculated based on its obstructions on metal1)

For example, to reproduce,

  1. Try to place a macro that has no OBS shapes on the first metal layer. -> replace exits complaining that the macro has no metal1 OBS statements.
  2. Insert a dummy OBS statement on metal1 (e.g., RECT 0 0 0 0 ;) -> replace reports such macros as having 0 height.

Thanks.

Release?

Hello, I am interested in packaging OpenROAD. This requires for a release to exist, so I was wondering if you have any plans about this? Perhaps a timeline?

Thanks,
Filipe

tapcell site misalign

Hello,

In some cases (which I don't what are the reasons behind them), tapcells are inserted in a location that is not aligned with sites. Please check with @tspyrou for a private repo with a test case.

Thanks,
kareem farid

Very long runtime for the report_checks command

Describe the bug
I try to implement an opensource FPGA with the openroad flow.
The report_checks command of the floorplan step was still not finished after 48 hours of execution.

The design is not so big (120k standard cells) but it contains many combinational feedback loops. Maybe this is what the STA tool doesn't like?

Expected behavior
A short runtime :)

Environment (please complete the following information):

  • OS: Archlinux (I know, not officially supported)
  • OpenROAD commit c60f972
  • OpenROAD-flow commit 229a1f4

File Uploads
The flow is available here https://git.slaanesh.org/killruana/openroad-flow-k1g100/src/branch/k1g100

$ git clone https://git.slaanesh.org/killruana/openroad-flow-k1g100
$ cd openroad-flow-k1g100
$ git checkout k1g100
$ cd flow
$ make DESIGN_CONFIG=designs/nangate45/k1g100.mk

I also join an archive:
k1g100.tar.gz

Additional context
Add any other context about the problem here.

Build Error in OpenRCX

I'm using SUSE Linux:

NAME="SLES"
VERSION="15-SP1"
VERSION_ID="15.1"
PRETTY_NAME="SUSE Linux Enterprise Server 15 SP1"
ID="sles"
ID_LIKE="suse"
ANSI_COLOR="0;32"
CPE_NAME="cpe:/o:suse:sles:15:sp1"

Here is the CMake output:

-- OpenROAD version: 1.0.1
-- OpenROAD git sha: bcc20ec161950770c1b013476ff11ed852434ad0
-- System name: Linux
-- Compiler: Clang 7.0.1
-- Build type: RELEASE
-- Build CXX_FLAGS: 
-- CXX_FLAGS: 
-- Install prefix: /usr/local
-- TCL library: /usr/lib64/libtcl8.6.so
-- TCL header: /usr/include/tcl.h
-- TCL library: /usr/lib64/libtcl8.6.so
-- TCL header: /usr/include/tcl.h
-- leflib_home: /home/ec2-user/OpenROAD/src/OpenDB/src/lef
-- STA version: 2.0.17
-- STA git sha: 25bf7b7ac87cd90d82a8e4ee18cf0a59d6e6530c
-- System name: Linux
-- Compiler: Clang 7.0.1
-- Build type: RELEASE
-- Build CXX_FLAGS: 
-- STA CXX_FLAGS: -Wall;-Wextra;-pedantic;-Wcast-qual;-Wredundant-decls;-Wformat-security;-Wno-deprecated-register
-- Install prefix: /usr/local
-- TCL library: /usr/lib64/libtcl8.6.so
-- TCL header: /usr/include/tcl.h
-- CUDD library: not found
-- SSTA: 0
-- STA executable: /home/ec2-user/OpenROAD/src/OpenSTA/app/sta
-- TCL lib: /usr/lib64/libtcl8.6.so
-- TCL header: /usr/include/tcl.h
-- Could NOT find Doxygen (missing: DOXYGEN_EXECUTABLE) 
-- Could NOT find Ghostscript (missing: GHOSTSCRIPT_EXECUTABLE) 
-- Could NOT find GLPK (missing: GLPK_LIBRARY GLPK_INCLUDE_DIR GLPK_PROPER_VERSION_FOUND) (Required is at least version "4.33")
-- Could NOT find ILOG (missing: ILOG_CPLEX_LIBRARY ILOG_CPLEX_INCLUDE_DIR) 
-- Could NOT find COIN (missing: COIN_INCLUDE_DIR COIN_CBC_LIBRARY COIN_CBC_SOLVER_LIBRARY COIN_CGL_LIBRARY COIN_CLP_LIBRARY COIN_COIN_UTILS_LIBRARY COIN_OSI_LIBRARY COIN_OSI_CBC_LIBRARY COIN_OSI_CLP_LIBRARY) 
-- Could NOT find SOPLEX (missing: SOPLEX_LIBRARY SOPLEX_INCLUDE_DIR) 
-- TCL library: /usr/lib64/libtcl8.6.so
-- TCL header: /usr/include/tcl.h
-- ABKCommon_home: /home/ec2-user/OpenROAD/src/TritonMacroPlace/module/ABKCommon
-- ParquetFP_home: /home/ec2-user/OpenROAD/src/TritonMacroPlace/module/ParquetFP
-- TCL library: /usr/lib64/libtcl8.6.so
-- TCL header: /usr/include/tcl.h
-- Configuring done
-- Generating done
-- Build files have been written to: /home/ec2-user/OpenROAD/build

I get the following error

/home/ec2-user/OpenROAD/src/OpenRCX/src/ext.cpp:45:36: error: cannot define or redeclare '_module' here because namespace 'OpenRCX' does not enclose namespace
      'ZTechModule<OpenRCX::Ext>'
const char* odb::ZTechModule<Ext>::_module = nullptr;

I'm attaching the full make output.
make.log

Error message is not immediately actionable "cannot insert center cellbuffer1 target (17964050 8801100)"

This error message needs to be a bit more understandable.

Is it a bug in the detailed placement? Any hints as to what to fix in my design?

I know the design fits...

Design area 393799 u^2 0% utilization.
openroad -no_init ./scripts/detail_place.tcl \
         2>&1 | tee ./logs/nangate45/AptosAvalonMMSlave/3_3_opendp.log
OpenROAD 1.1.0 
License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Notice 0: Reading LEF file:  ./objects/nangate45/AptosAvalonMMSlave/merged_padded.lef
Notice 0:     Created 22 technology layers
Notice 0:     Created 27 technology vias
Notice 0:     Created 134 library cells
Notice 0: Finished LEF file:  ./objects/nangate45/AptosAvalonMMSlave/merged_padded.lef
Notice 0: 
Reading DEF file: ./results/nangate45/AptosAvalonMMSlave/3_2_place_resized.def
Notice 0: Design: AptosAvalonMMSlave
Notice 0: 		Created 100000 Insts
Notice 0: 		Created 200000 Insts
Notice 0: lines processed: 1000000
Notice 0: lines processed: 2000000
Notice 0: lines processed: 3000000
Notice 0: lines processed: 4000000
Notice 0: lines processed: 5000000
Notice 0: lines processed: 6000000
Notice 0: lines processed: 7000000
Notice 0:     Created 5070 pins.
Notice 0:     Created 253063 components and 569150 component-terminals.
Notice 0:     Created 2 special nets and 506126 connections.
Notice 0:     Created 27440 nets and 63024 connections.
Notice 0: Finished DEF file: ./results/nangate45/AptosAvalonMMSlave/3_2_place_resized.def
-------------------- Design Stats ------------------------------
core area                  : (40280, 44800) (17246680, 17236800)
total cells                : 253063
multi cells                : 0
fixed cells                : 230321
nets                       : 27442
design area                : 2.96e+14
total fixed area           : 2.45e+11
total movable area         : 3.42e+11
design utilization         : 0.116
rows                       : 6140
row height                 : 2800
----------------------------------------------------------------
Error: cannot insert center cellbuffer1 target (17964050 8801100)
Error: cannot insert center cellbuffer2 target (17964050 4924220)
...
[deleted]
Check Legality
row check ==> PASS 
site check ==> PASS 
power check ==> PASS 
edge_check ==> PASS 
placed_check ==> FAIL (1461)
overlap_check ==> FAIL 
-------------------- Placement Analysis ------------------------
total displacement         : 1711741403
average displacement       : 6764
max displacement           : 35950830
original HPWL              : 2.21e+07
legalized HPWL             : 5.08e+07
delta HPWL                 : 130%
----------------------------------------------------------------
Error: cannot insert center cellbuffer1 target (17964050 8801100)
...
[deleted]
make: *** [results/nangate45/AptosAvalonMMSlave/3_3_place_dp.def] Error 1

real	96m51,083s
user	0m0,873s
sys	0m0,627s

0 solutions found on a trivial design

Hello,
TritonMacroPlace doesn't find solutions on a trivial design with only 1 macro.

Screenshot: https://user-images.githubusercontent.com/19731159/70730282-5ec57280-1d0d-11ea-8cd3-d59e820781d6.png

Things tried:

  • padding the macro so that its width and height are multiple of a site width and height
    trivial (empty) sdc file
  • reducing halo and channel widths down to very low values (1)
  • reducing utilization down to 10%
  • removing all stdcells before running mplace:

Screenshot: https://user-images.githubusercontent.com/19731159/70730280-5ec57280-1d0d-11ea-878d-25e03c49618f.png

All still lead to 0 solutions

Log file and script used: mplace.zip

I know screenshots aren't the best way to fully communicate the issue. So, please let me know if further information is needed.

Thanks!

Synthesis of small circuits

Greetings,

I am trying to synthesize small circuits like multipliers. In one tool (QFLOW) my designs exhibit really small energy consumption. On the other hand OpenROAD, I get totally different results. Can you give some tips on how to efficiently synthesize small designs?

Ratko

OpenROAD is crashing while starting FastRoute

OpenROAD is crashing while starting FastRoute for https://github.com/tamimcse/test/blob/master/top.v. The Verilog is generated using Bambu HLS. The OpenROAD script is https://github.com/tamimcse/test/blob/master/bash_script.sh. The output is as following: You will see the crash at the very end.

.....
......
yosys> opt_clean -purge

Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy..
Removed 96 unused cells and 9494 unused wires.
<suppressed ~183 debug messages>
y_typical.lib iberty /opt/panda/share/panda//nangate45/lib/NangateOpenCellLibrary

Printing statistics.
=== _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy ===

Number of wires: 20066
Number of wire bits: 21196
Number of public wires: 2469
Number of public wire bits: 3599
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 18580
AND2_X1 1925
AND2_X2 49
AND2_X4 45
AND3_X1 488
AND3_X2 3
AND3_X4 6
AND4_X1 120
AND4_X2 3
AND4_X4 3
AOI211_X1 272
AOI211_X2 3
AOI21_X1 882
AOI21_X2 3
AOI221_X1 1
AOI221_X2 2
AOI221_X4 33
AOI22_X1 22
BUF_X1 4070
BUF_X16 2
BUF_X2 115
BUF_X4 273
BUF_X8 5
CLKBUF_X2 58
CLKBUF_X3 3
DFF_X1 1514
INV_X1 807
INV_X2 18
INV_X32 5
INV_X4 6
LOGIC0_X1 1
MUX2_X1 1143
MUX2_X2 4
NAND2_X1 1288
NAND2_X2 3
NAND2_X4 1
NAND3_X1 451
NAND3_X2 1
NAND4_X1 84
NAND4_X2 1
NOR2_X1 1262
NOR2_X2 11
NOR2_X4 9
NOR3_X1 335
NOR3_X2 1
NOR3_X4 1
NOR4_X1 58
NOR4_X2 2
NOR4_X4 2
OAI211_X1 356
OAI211_X2 3
OAI21_X1 615
OAI21_X2 1
OAI221_X1 44
OAI22_X1 30
OAI22_X2 1
OR2_X1 228
OR2_X2 5
OR2_X4 2
OR3_X1 236
OR4_X1 111
OR4_X2 1
XNOR2_X1 668
XOR2_X1 873
XOR2_X2 12

Chip area for module '_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy': 25630.164000

S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy_mapped.vPhPtS_PjS_S1_S_S1_S_S1
21. Executing Verilog backend.
Dumping module `_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy'.

yosys> exit

Warnings: 8 unique messages, 72 total
End of script. Logfile hash: 9dd2f6b66b, CPU: user 35.81s system 0.18s, MEM: 104.99 MB peak
Yosys 0.9+1706 (git sha1 b7419544, gcc 7.4.0-1ubuntu1~18.04.1 -fPIC -Os)
Time spent: 28% 30x opt_clean (9 sec), 17% 25x opt_merge (6 sec), ...
OpenROAD 1.1.0 484b8f0
License GPLv3: GNU GPL version 3 http://gnu.org/licenses/gpl.html

This is free software, and you are free to change and redistribute it
under certain conditions; type show_copying' for details. This program comes with ABSOLUTELY NO WARRANTY; for details type show_warranty'.
Notice 0: Reading LEF file: OpenROAD_objects/merged.lef
Notice 0: Created 22 technology layers
Notice 0: Created 27 technology vias
Notice 0: Created 134 library cells
Notice 0: Finished LEF file: OpenROAD_objects/merged.lef
Startpoint: 34756 (rising edge-triggered flip-flop clocked by clock)
Endpoint: 36070 (rising edge-triggered flip-flop clocked by clock)
Path Group: clock
Path Type: max

Delay Time Description
0.00 0.00 clock clock (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ 34756/CK (DFF_X1)
0.08 0.08 ^ 34756/Q (DFF_X1)
0.17 0.26 ^ 30643/Z (BUF_X1)
0.02 0.28 v 17612/ZN (NOR2_X4)
0.05 0.33 v 17614/ZN (AND2_X4)
0.03 0.36 ^ 17703/ZN (NOR2_X2)
0.02 0.38 v 17719/ZN (INV_X1)
0.05 0.43 ^ 17720/ZN (AOI221_X2)
0.04 0.47 ^ 17721/ZN (AND2_X2)
0.03 0.50 ^ 17727/ZN (AND2_X4)
0.03 0.53 ^ 17749/ZN (AND2_X4)
0.03 0.56 ^ 17750/Z (BUF_X4)
0.04 0.59 ^ 21064/ZN (AND3_X4)
0.04 0.64 ^ 21069/ZN (AND3_X2)
0.04 0.67 ^ 21345/ZN (AND2_X4)
0.03 0.70 ^ 21451/Z (BUF_X8)
0.06 0.76 v 21452/Z (MUX2_X1)
0.03 0.79 v 21453/ZN (AND2_X1)
0.06 0.85 ^ 21456/ZN (AOI211_X2)
0.01 0.86 v 21467/ZN (NOR3_X1)
0.04 0.90 v 21487/ZN (OR2_X1)
0.06 0.96 v 21488/Z (MUX2_X1)
0.03 0.98 v 32559/Z (BUF_X1)
0.00 0.98 v 36070/D (DFF_X1)
0.98 data arrival time

1.00 1.00 clock clock (rise edge)
0.00 1.00 clock network delay (ideal)
0.00 1.00 clock reconvergence pessimism
1.00 ^ 36070/CK (DFF_X1)
-0.04 0.96 library setup time
0.96 data required time
0.96 data required time
-0.98 data arrival time
-0.02 slack (VIOLATED)
Design area 102521 u^2 100% utilization.
Info: Added 428 rows of 3158 sites.
WARNING: force pin spread option has no effect when using random pin placement

Running IO placement

Num of slots 7698
Num of I/O 1173
Num of I/O w/sink 1130
Num of I/O w/o sink 43
Slots Per Section 200
Slots Increase Factor 0.01
Usage Per Section 0.8
Usage Increase Factor 0.01
Force Pin Spread 1
WARNING: running random pin placement
RandomMode Even

IO placement done.
OpenROAD 1.1.0 484b8f0
License GPLv3: GNU GPL version 3 http://gnu.org/licenses/gpl.html

This is free software, and you are free to change and redistribute it
under certain conditions; type show_copying' for details. This program comes with ABSOLUTELY NO WARRANTY; for details type show_warranty'.
Notice 0: Reading LEF file: OpenROAD_objects/merged_padded.lef
Notice 0: Created 22 technology layers
Notice 0: Created 27 technology vias
Notice 0: Created 134 library cells
Notice 0: Finished LEF file: OpenROAD_objects/merged_padded.lef
Notice 0:
Reading DEF file: OpenROAD_results/2_2_floorplan_io.def
Notice 0: Design: _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
Notice 0: Created 1173 pins.
Notice 0: Created 18580 components and 95604 component-terminals.
Notice 0: Created 21186 nets and 58444 connections.
Notice 0: Finished DEF file: OpenROAD_results/2_2_floorplan_io.def
invalid command name "STEP 3: Timing Driven Mixed Sized Placement"
No macros found: Skipping global_placement
fixIoPins.py : Fixing Pins in Def file
Replacements made - West:337 South:249 East:338 North:249
fixIoPins.py : Finished
OpenROAD 1.1.0 484b8f0
License GPLv3: GNU GPL version 3 http://gnu.org/licenses/gpl.html

This is free software, and you are free to change and redistribute it
under certain conditions; type show_copying' for details. This program comes with ABSOLUTELY NO WARRANTY; for details type show_warranty'.
Notice 0: Reading LEF file: OpenROAD_objects/merged_padded.lef
Notice 0: Created 22 technology layers
Notice 0: Created 27 technology vias
Notice 0: Created 134 library cells
Notice 0: Finished LEF file: OpenROAD_objects/merged_padded.lef
Notice 0:
Reading DEF file: OpenROAD_results/2_3_floorplan_tdms.def
Notice 0: Design: _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
Notice 0: Created 1173 pins.
Notice 0: Created 18580 components and 95604 component-terminals.
Notice 0: Created 21186 nets and 58444 connections.
Notice 0: Finished DEF file: OpenROAD_results/2_3_floorplan_tdms.def
No macros found: Skipping macro_placement
##Power Delivery Network Generator: Generating PDN

config: /opt/panda/share/panda//nangate45/pdn.cfg
Design Name is _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
Reading BEOL LEF and gathering information ...
****** INFO ******
Type: stdcell, grid
Stdcell Rails
Layer: metal1 - Width: 0.170 Pitch: 2.400 Offset: 0.000
Straps
Layer: metal4 - Width: 0.480 Pitch: 56.000 Offset: 2.000
Layer: metal7 - Width: 1.400 Pitch: 40.000 Offset: 2.000
Connect: {metal1 metal4} {metal4 metal7}
Type: macro, macro_1
Macro orientation: R0 R180 MX MY
Straps
Layer: metal5 - Width: 0.930 Pitch: 40.000 Offset: 2.000
Layer: metal6 - Width: 0.930 Pitch: 40.000 Offset: 2.000
Connect: {metal4_PIN_ver metal5} {metal5 metal6} {metal6 metal7}
Type: macro, macro_2
Macro orientation: R90 R270 MXR90 MYR90
Straps
Layer: metal6 - Width: 0.930 Pitch: 40.000 Offset: 2.000
Connect: {metal4_PIN_hor metal6} {metal6 metal7}
**** END INFO ****
Inserting stdcell grid - grid
Writing to database
Running tapcell...
Step 1: Cut rows...
---- Macro blocks found: 0
---- #Original rows: 428
---- #Cut rows: 0
Step 2: Insert endcaps...
---- #Endcaps inserted: 856
Step 3: Insert tapcells...
---- #Tapcells inserted: 860
Running tapcell... Done!
[INFO] TargetDensity = 0.700000
mkdir: cannot create directory ‘/dev/null’: Not a directory
mkdir: cannot create directory ‘/dev/null’: Not a directory
mkdir: cannot create directory ‘/dev/null’: Not a directory
mkdir: cannot create directory ‘/dev/null’: Not a directory
mkdir: cannot create directory ‘/dev/null’: Not a directory
mkdir: cannot create directory ‘/dev/null’: Not a directory
[PROC] Begin Filling Replace Structure ...
[INFO] DEF DBU = 2000
[INFO] RowHeight = 2800.000000
[INFO] ScaleDownUnit = 311.111115
[INFO] CoreAreaLxLy = (20140.000000, 22400.000000)
[INFO] CoreAreaUxUy = (1220180.000000, 1220800.000000)
[INFO] OffsetCoordi = (2260.000000, 0.000000)
[INFO] ScaleDownRowHeight = 9.000000
[INFO] Modules = 18580
[INFO] Terminals = 2889
[PROC] Begin Generate Nets ...
[INFO] NumNets = 21186
[INFO] NumPins = 59617
[PROC] End Generate Nets
[INFO] Inserted Dummy Terms = 0
[PROC] Begin Generate Rows ...
[INFO] RowSize = (1.221429, 9.000000)
[INFO] NumRows = 428
[PROC] End Generate Rows
[INFO] AspectRatio = 0.998633
[INFO] RowMinXY = (72.000000, 79.264282)
[INFO] RowMaxXY = (3929.271240, 3931.264160)
[INFO] NumPlaceStdCells = 18580
[INFO] NumPlaceMacros = 0
[INFO] RowSize = (1.221429, 9.000000)
[INFO] NumRows = 428
[INFO] GlobalAreaLxLy = (7.489285, 7.489285)
[INFO] GlobalAreaUxUy = (3993.717773, 3996.610596)
[INFO] PlaceAreaLxLy = (72.000000, 79.264160)
[INFO] PlaceAreaUxUy = (3929.271240, 3931.264160)
[PROC] End Filling Replace Structure
PROC: Conjugate Gradient (CG) method to obtain the IP
INFO: The Initial HPWL is 524644.543317
INFO: The Matrix Size is 18580
INFO: IP 0, CG Error 0.000027, HPWL 545957.517281, CPUtime 0.17
INFO: IP 1, CG Error 0.000006, HPWL 526126.977911, CPUtime 0.21
INFO: IP 2, CG Error 0.000001, HPWL 523085.066241, CPUtime 0.22
INFO: IP 3, CG Error 0.000001, HPWL 522274.195831, CPUtime 0.21
INFO: IP 4, CG Error 0.000001, HPWL 521964.732325, CPUtime 0.19
INFO: IP 5, CG Error 0.000000, HPWL 521564.830225, CPUtime 0.21
===HPWL(MICRON)====================================
Mode : Initial Placement
HPWL : 735601.8216
x= 369036.8821 y= 366564.9395
[INFO] TotalPlaceArea = 14858209.000000
[INFO] TotalFixedArea = 18862.050781
[INFO] TotalWhiteSpaceArea = 14839347.000000
[INFO] TotalPlaceMacrosArea = 0.000000
[INFO] TotalPlaceStdCellsArea = 2692896.250000
[INFO] Util(%) = 18.123962
[INFO] 80pCellArea = 139.526581
[INFO] FillerInit: TotalFillerArea = 7694647.000000
[INFO] FillerInit: NumFillerCells = 55146
[INFO] FillerInit: FillerCellArea = 139.533539
[INFO] FillerInit: FillerCellSize = (15.503726, 9.000000)
[INFO] FillerInit: NumCells = 73726
[INFO] FillerInit: NumModules = 18580
[INFO] FillerInit: NumFillers = 55146
INFO: D_MSH = 1024
INFO: MSH(X, Y) = (32, 32)
INFO: dim_bin_cGP2D.(x,y) = (256, 256)
cell Init 2D:
tier->bin_stp: (15.0675 15.0469)
tier->half_bin_stp: (7.5337 7.5234)
PROC: Start NESTEROV's Optimization
PROC: Global Lagrangian Multiplier is Applied
[INFO] Timing: WNS = 1.29948e-11
[INFO] Timing: TNS = 0
[INFO] Nesterov: 0 OverFlow: 0.9854 ScaledHpwl: 3353720.0000
[INFO] Timing: WNS = -9.08862e-12
[INFO] Timing: TNS = -1.37044e-11
[INFO] Nesterov: 10 OverFlow: 0.7612 ScaledHpwl: 4656717.5000
[INFO] Nesterov: 20 OverFlow: 0.7271 ScaledHpwl: 4600205.0000
[INFO] Nesterov: 30 OverFlow: 0.7259 ScaledHpwl: 4532463.0000
[INFO] Nesterov: 40 OverFlow: 0.7285 ScaledHpwl: 4490022.5000
[INFO] Nesterov: 50 OverFlow: 0.7235 ScaledHpwl: 4512176.5000
[INFO] Nesterov: 60 OverFlow: 0.7214 ScaledHpwl: 4498370.5000
[INFO] Nesterov: 70 OverFlow: 0.7225 ScaledHpwl: 4486582.0000
[INFO] Nesterov: 80 OverFlow: 0.7223 ScaledHpwl: 4493103.0000
[INFO] Nesterov: 90 OverFlow: 0.7214 ScaledHpwl: 4493090.0000
[INFO] Nesterov: 100 OverFlow: 0.7219 ScaledHpwl: 4488126.0000
[INFO] Nesterov: 110 OverFlow: 0.7223 ScaledHpwl: 4489798.5000
[INFO] Nesterov: 120 OverFlow: 0.7219 ScaledHpwl: 4492216.0000
[INFO] Nesterov: 130 OverFlow: 0.7219 ScaledHpwl: 4491156.5000
[INFO] Nesterov: 140 OverFlow: 0.7219 ScaledHpwl: 4491949.0000
[INFO] Nesterov: 150 OverFlow: 0.7213 ScaledHpwl: 4494138.0000
[INFO] Nesterov: 160 OverFlow: 0.7207 ScaledHpwl: 4495404.0000
[INFO] Nesterov: 170 OverFlow: 0.7195 ScaledHpwl: 4498037.5000
[INFO] Nesterov: 180 OverFlow: 0.7177 ScaledHpwl: 4502708.0000
[INFO] Nesterov: 190 OverFlow: 0.7145 ScaledHpwl: 4507794.5000
[INFO] Nesterov: 200 OverFlow: 0.7106 ScaledHpwl: 4516302.0000
[INFO] Nesterov: 210 OverFlow: 0.7026 ScaledHpwl: 4528353.0000
[INFO] Nesterov: 220 OverFlow: 0.6926 ScaledHpwl: 4537470.5000
[INFO] Nesterov: 230 OverFlow: 0.6770 ScaledHpwl: 4543792.0000
[INFO] Nesterov: 240 OverFlow: 0.6535 ScaledHpwl: 4535685.5000
[INFO] Timing: WNS = -5.55014e-11
[INFO] Timing: TNS = -5.22214e-10
[INFO] Nesterov: 250 OverFlow: 0.6285 ScaledHpwl: 4530373.0000
[INFO] Nesterov: 260 OverFlow: 0.5989 ScaledHpwl: 4576544.0000
[INFO] Nesterov: 270 OverFlow: 0.5632 ScaledHpwl: 4603646.0000
[INFO] Nesterov: 280 OverFlow: 0.5264 ScaledHpwl: 4607634.0000
[INFO] Nesterov: 290 OverFlow: 0.4824 ScaledHpwl: 4654078.0000
[INFO] Timing: WNS = -1.06277e-10
[INFO] Timing: TNS = -2.22512e-09
[INFO] Nesterov: 300 OverFlow: 0.4519 ScaledHpwl: 4672081.0000
[INFO] Nesterov: 310 OverFlow: 0.4206 ScaledHpwl: 4691820.0000
[INFO] Nesterov: 320 OverFlow: 0.3851 ScaledHpwl: 4693493.0000
[INFO] Nesterov: 330 OverFlow: 0.3558 ScaledHpwl: 4698090.0000
[INFO] Nesterov: 340 OverFlow: 0.3219 ScaledHpwl: 4705394.0000
[INFO] Nesterov: 350 OverFlow: 0.2854 ScaledHpwl: 4708784.0000
[INFO] Timing: WNS = -1.50303e-10
[INFO] Timing: TNS = -2.67458e-09
[INFO] Nesterov: 360 OverFlow: 0.2545 ScaledHpwl: 4708413.0000
[INFO] Nesterov: 370 OverFlow: 0.2222 ScaledHpwl: 4707805.5000
[INFO] Timing: WNS = -1.4887e-10
[INFO] Timing: TNS = -2.59766e-09
[INFO] Nesterov: 380 OverFlow: 0.1903 ScaledHpwl: 4707631.5000
[INFO] Nesterov: 390 OverFlow: 0.1622 ScaledHpwl: 4708060.5000
[INFO] Nesterov: 400 OverFlow: 0.1380 ScaledHpwl: 4708762.5000
[INFO] Nesterov: 410 OverFlow: 0.1158 ScaledHpwl: 4712566.5000
[INFO] Nesterov: 420 OverFlow: 0.0998 ScaledHpwl: 4717579.5000
[INFO] Timing: WNS = -1.53279e-10
[INFO] Timing: TNS = -2.60917e-09
HP wire length: 731895
Worst slack: -1.53e-01
Total negative slack: -2.61e+00
Warning: cell 'OAI211_X1}' not found.
Error: get_property is not an object.
Inserted 1091 input buffers.
Inserted 81 output buffers.
Resized 5488 instances.
Inserted 0 hold buffers.
-------------------- Design Stats ------------------------------
core area : (20140, 22400) (1220180, 1220800)
total cells : 21468
multi cells : 0
fixed cells : 1716
nets : 22360
design area : 1438127936000.000
total fixed area : 1825824000.000
total movable area : 284683840000.000
design utilization : 19.821
rows : 428
row height : 2800
Check Legality
row check ==> PASS
site check ==> PASS
power check ==> PASS
edge_check ==> PASS
placed_check ==>> PASS
overlap_check ==> PASS
-------------------- Placement Analysis ------------------------
total displacement : 62095532
average displacement : 2892
max displacement : 66070
original HPWL : 738875.682
legalized HPWL : 752026.493
delta HPWL : 2%
TritonCTS 2.0 *
Current time: Thu Mar 19 22:26:59 2020

Import characterization *
Reading LUT file "/opt/panda/share/panda//nangate45/tritonCTS/lut.txt"
Min. len Max. len Min. cap Max. cap Min. slew Max. slew
2 8 1 52 1 24
[WARNING] 180 wires are pure wire and no slew degration.
TritonCTS forced slew degradation on these wires.
Num wire segments: 4994
Num keys in characterization LUT: 1677
Actual min input cap: 8
Reading solution list file "/opt/panda/share/panda//nangate45/tritonCTS/sol_list.txt"

Find clock roots *
User did not specify clock roots.
Using OpenSTA to find clock roots.
Looking for clock sources...
Clock names: clock

Populate TritonCTS *
Initializing clock nets
Number of user-input clocks: 1 ( "clock" )
Looking for clock nets in the design
Net "clock" found
clock

Check characterization *
The chacterization used 1 buffer(s) types. All of them are in the loaded DB.
Build clock trees *
Generating H-Tree topology for net clock...
Tot. number of sinks: 1514
Wire segment unit: 20000 dbu (10 um)
Original sink region: [(231990, 315170), (972610, 919970)]
Normalized sink region: [(12, 16), (49, 46)]
Width: 37
Height: 30
Level 1
Direction: Horizontal

sinks per sub-region: 757
Sub-region size: 19 X 30
Segment length (rounded): 10
Key: 3192 outSlew: 1 load: 1 length: 8 isBuffered: 1
Key: 0 outSlew: 2 load: 1 length: 2 isBuffered: 0
Level 2
Direction: Vertical

sinks per sub-region: 379
Sub-region size: 19 X 15
Segment length (rounded): 8
Key: 3206 outSlew: 1 load: 1 length: 8 isBuffered: 1
Level 3
Direction: Horizontal

sinks per sub-region: 190
Sub-region size: 9 X 15
Segment length (rounded): 4
Key: 1170 outSlew: 12 load: 1 length: 4 isBuffered: 1
Level 4
Direction: Vertical

sinks per sub-region: 95
Sub-region size: 9 X 8
Segment length (rounded): 4
Key: 1242 outSlew: 12 load: 1 length: 4 isBuffered: 1
Level 5
Direction: Horizontal

sinks per sub-region: 48
Sub-region size: 5 X 8
Segment length (rounded): 2
Key: 548 outSlew: 2 load: 1 length: 2 isBuffered: 1
[WARNING] Creating fake entries in the LUT.
Level 6
Direction: Vertical

sinks per sub-region: 24
Sub-region size: 5 X 4
Segment length (rounded): 1
Key: 5029 outSlew: 12 load: 1 length: 1 isBuffered: 1
Level 7
Direction: Horizontal

sinks per sub-region: 12
Sub-region size: 2 X 4
Segment length (rounded): 1
Key: 5039 outSlew: 12 load: 1 length: 1 isBuffered: 1
Stop criterion found. Max number of sinks is (15)
Building clock sub nets...
Number of sinks covered: 1514
Clock topology of net "clock" done.

Post CTS opt *
Avg. source sink dist: 46402 dbu.
Num outlier sinks: 3

Write data to DB *
Writing clock net "clock" to DB
Created 258 clock buffers.
Created 258 clock nets.

Current time: Thu Mar 19 22:26:59 2020
... End of TritonCTS execution.
-------------------- Design Stats ------------------------------
core area : (20140, 22400) (1220180, 1220800)
total cells : 21726
multi cells : 0
fixed cells : 1716
nets : 22618
design area : 1438127936000.000
total fixed area : 1825824000.000
total movable area : 287720496000.000
design utilization : 20.032
rows : 428
row height : 2800
Check Legality
row check ==> PASS
site check ==> PASS
power check ==> PASS
edge_check ==> PASS
placed_check ==>> PASS
overlap_check ==> PASS
-------------------- Placement Analysis ------------------------
total displacement : 1657681
average displacement : 76
max displacement : 16853
original HPWL : 763228.133
legalized HPWL : 763580.620
delta HPWL : 0%
Adjust layer 2 in 70.0%
Adjust layer 3 in 70.0%
*** buffer overflow detected ***: openroad terminated

OpenDP bug in filler_placement with set_placement_padding

padding_filler
padding_filler2

The filler_placement command with set_placement_padding generated overlapped placement result.

There are overlapped cells after OpenDP.
I attached Innovus checkPlace results that contains a list of overlapped cells (bug02_result.rpt).

Could you check the attached testcase?

bug02.tar.gz

I used the following commit in OpenROAD repo:
4187ce7

Thanks,

Unmentioned and uninstallable dependencies

Thanks for the prompt response on the git clone problem.

I am still attempting to compile from source. On doing cmake, I get complaints about not finding these dependencies, which are not mentioned in the dependency list in the README file:

GLPK, ILOG, COIN, SOPLEX

For the first one, I tried "apt install libglpk-dev" but got back:
libglpk-dev : Depends: libgmp-dev but it is not going to be installed
Depends: libsuitesparse-dev but it is not going to be installed

The others do not appear to be things that can be obtained using yum or apt.
Thoughts?
---Tim

plist problems: Installs bundled dependencies and causes conflicts with preinstalled packages

The installed plist looks like this:

bin/openroad
bin/sta
include/ArcDelayCalc.hh
include/Arnoldi.hh
<...more OpenSTA headers...>

The above conflict with a separate opensta package.

include/lemon/adaptors.h
include/lemon/arg_parser.h
<...more lemon headers...>

these conflict with the separate lemon package.

/usr/ports/cad/openroad/work/.OpenPhySyn/transforms/libbuffer_fanout.a
/usr/ports/cad/openroad/work/.OpenPhySyn/transforms/libconstant_propagation.a
/usr/ports/cad/openroad/work/.OpenPhySyn/transforms/libgate_clone.a
/usr/ports/cad/openroad/work/.OpenPhySyn/transforms/libpin_swap.a
@dir /usr/ports/cad/openroad/work/.OpenPhySyn/transforms
@dir /usr/ports/cad/openroad/work/.OpenPhySyn
@dir /usr/ports/cad/openroad/work
@dir /usr/ports/cad/openroad
@dir /usr/ports/cad
@dir /usr/ports

The above files are installed into obviously wrong paths.


The above problems result from bundling used in the project. Please consider having cmake options to use separate packages when they are available.

Setting up enviroment for hardware designer is little bit challanging

I have attended VLSID2020 in Bangalore, where I build my interest to work on OpenROAD Project.

I am hardware designer having background of Physical Design and Timing Checks.With the help of Presenters ,I cloned the different packages like OpenRoad, OpeRoadSTA, Yosys for PnR, Timing Analysis and Synthesis respectively.

I found it little tricky to setup the build environment to start working on project.If this could be resolved it will be easy to go through in further steps.

Can we have pre-built binaries for all the tool which require to execute frontend and backend flow in VLSI?

tritonMacroplace liberty /.lib dependance

Hello,

It seems that tritonMacroplace depends on defining all the design cells and macros in a .lib and needs to be read using read_liberty. Otherwise, it crashes after outputting Generating Sequantial Graph.... To replicate this, simply omit one of the read lib in tritonMacroplace test cases.

Thanks

Build fails in Ubuntu

For collaboration purposes, I do think it should be possible to build OpenROAD from source. Log file based on following README file below. I am guessing dependancy issues, but there are no extract requirementsgiven, so not sure how to reproduce build.

-- OpenROAD version: 1.0.1
-- System name: Linux
-- Compiler: GNU 7.4.0
-- Build type: RELEASE
-- Build CXX_FLAGS: -O3 -DNDEBUG
-- CXX_FLAGS:
-- Install prefix: /usr/local
-- TCL lib: /usr/lib/x86_64-linux-gnu/libtcl.so
-- TCL header: /usr/include/tcl/tcl.h
-- STA version: 2.0.17
-- System name: Linux
-- Compiler: GNU 7.4.0
-- Build type: RELEASE
-- Build CXX_FLAGS: -O3 -DNDEBUG
-- STA CXX_FLAGS: -Wall;-Wextra;-pedantic;-Wcast-qual;-Wredundant-decls;-Wformat-security
-- Install prefix: /usr/local
-- CUDD library: not found
-- SSTA: 0
-- TCL lib: /usr/lib/x86_64-linux-gnu/libtcl.so
-- TCL header: /usr/include/tcl/tcl.h
-- STA executable: /home/aolofsson/work/darpa/IDEA/ucsd-openroad/OpenROAD/src/OpenSTA/app/sta
-- ioPlacer
-- /home/aolofsson/work/darpa/IDEA/ucsd-openroad/OpenROAD/src/ioPlacer
INFO: RELEASE BUILD
-- Boost version: 1.65.1
-- TCL lib: /usr/lib/x86_64-linux-gnu/libtcl.so
-- TCL header: /usr/include/tcl/tcl.h
-- Found GLPK: /usr/lib/x86_64-linux-gnu/libglpk.so (Required is at least version "4.33")
-- Could NOT find ILOG (missing: ILOG_CPLEX_LIBRARY ILOG_CPLEX_INCLUDE_DIR)
-- Could NOT find COIN (missing: COIN_INCLUDE_DIR COIN_CBC_LIBRARY COIN_CBC_SOLVER_LIBRARY COIN_CGL_LIBRARY COIN_CLP_LIBRARY COIN_COIN_UTILS_LIBRARY COIN_OSI_LIBRARY COIN_OSI_CBC_LIBRARY COIN_OSI_CLP_LIBRARY)
-- Could NOT find SOPLEX (missing: SOPLEX_LIBRARY SOPLEX_INCLUDE_DIR)
CMake Error at src/CMakeLists.txt:132 (add_subdirectory):
The source directory

/home/aolofsson/work/darpa/IDEA/ucsd-openroad/OpenROAD/src/FastRoute

does not contain a CMakeLists.txt file.

CMake Error at src/CMakeLists.txt:134 (add_subdirectory):
The source directory

/home/aolofsson/work/darpa/IDEA/ucsd-openroad/OpenROAD/src/TritonMacroPlace

does not contain a CMakeLists.txt file.

-- Configuring incomplete, errors occurred!
See also "/home/aolofsson/work/darpa/IDEA/ucsd-openroad/OpenROAD/build/CMakeFiles/CMakeOutput.log".

Empty segment vector

I'm getting the following error for https://github.com/tamimcse/test5 (compiled openroad with compiler optimization off, otherwise it crashes while starting FastRoute).

17. Printing statistics.

=== _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy ===

   Number of wires:              13443
   Number of wire bits:          14573
   Number of public wires:        2460
   Number of public wire bits:    3590
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              11967
     AND2_X1                       388
     AND2_X2                        31
     AND2_X4                         5
     AND3_X1                        64
     AND3_X2                         3
     AND3_X4                         3
     AND4_X1                         3
     AOI211_X2                      25
     AOI21_X1                      905
     AOI21_X2                      221
     AOI21_X4                       53
     AOI221_X1                      63
     AOI221_X2                      13
     AOI222_X1                       1
     AOI22_X1                      152
     BUF_X1                        580
     BUF_X2                         12
     BUF_X4                         25
     CLKBUF_X1                     122
     CLKBUF_X2                     196
     DFF_X1                       1514
     INV_X1                        264
     INV_X2                          2
     LOGIC0_X1                       1
     MUX2_X1                      1533
     MUX2_X2                         7
     NAND2_X1                     1067
     NAND2_X2                       12
     NAND2_X4                        4
     NAND3_X1                      128
     NAND3_X2                        9
     NAND3_X4                        2
     NAND4_X1                       26
     NAND4_X2                        1
     NOR2_X1                      1200
     NOR2_X2                        34
     NOR2_X4                         4
     NOR3_X1                       145
     NOR3_X2                         8
     NOR3_X4                         1
     NOR4_X1                        47
     NOR4_X2                         1
     OAI211_X2                       3
     OAI211_X4                       1
     OAI21_X1                      609
     OAI21_X2                      232
     OAI21_X4                       36
     OAI221_X1                      84
     OAI221_X2                       1
     OAI22_X1                       93
     OAI33_X1                        3
     OR2_X1                        312
     OR2_X2                         13
     OR2_X4                         13
     OR3_X1                         28
     OR3_X2                          2
     OR3_X4                          3
     OR4_X1                         24
     XNOR2_X1                      964
     XNOR2_X2                        2
     XOR2_X1                       664
     XOR2_X2                         5

   Chip area for module '\_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy': 20108.004000

18. Executing Verilog backend.
Dumping module `\_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy'.

Warnings: 13 unique messages, 77 total
End of script. Logfile hash: ff77991497, CPU: user 22.12s system 0.08s, MEM: 114.82 MB peak
Yosys 0.9+1706 (git sha1 b7419544, gcc 7.4.0-1ubuntu1~18.04.1 -fPIC -Os)
Time spent: 25% 27x opt_clean (5 sec), 19% 25x opt_merge (4 sec), ...
0:25.97elapsed 99%CPU 117584memKB
mkdir -p ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy ./logs/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy ./reports/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
cp results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/1_1_yosys.v results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/1_synth.v
mkdir -p ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy ./logs/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy ./reports/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
cp designs/src/sail/sail.sdc results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/1_synth.sdc
(/usr/bin/time -f "%Eelapsed %PCPU %MmemKB" openroad -no_init -exit ./scripts/floorplan.tcl) 2>&1 | tee ./logs/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/2_1_floorplan.log
OpenROAD 1.1.0 ef1118f201
License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0:     Created 22 technology layers
Notice 0:     Created 27 technology vias
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0:     Created 134 library cells
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Info: Added 592 rows of 4369 sites.

==========================================================================
report_checks
--------------------------------------------------------------------------
Startpoint: _21751_ (rising edge-triggered flip-flop clocked by core_clock)
Endpoint: _21813_ (rising edge-triggered flip-flop clocked by core_clock)
Path Group: core_clock
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock core_clock (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 ^ _21751_/CK (DFF_X1)
   0.08    0.08 v _21751_/Q (DFF_X1)
   0.03    0.11 v _12699_/Z (BUF_X4)
   0.02    0.13 ^ _17174_/ZN (NOR2_X2)
   0.02    0.15 v _17175_/ZN (OAI21_X2)
   0.11    0.26 ^ _17185_/ZN (AOI221_X1)
   0.02    0.28 v _17189_/ZN (NOR3_X2)
   0.04    0.32 ^ _17191_/ZN (OAI21_X2)
   0.02    0.34 v _17196_/ZN (AOI21_X2)
   0.06    0.40 ^ _17199_/ZN (AOI21_X1)
   0.03    0.43 v _17205_/ZN (AOI21_X2)
   0.02    0.45 ^ _17208_/ZN (NAND2_X2)
   0.01    0.46 v _17214_/ZN (AOI21_X2)
   0.06    0.53 ^ _17215_/ZN (AOI21_X1)
   0.03    0.55 v _17219_/ZN (OAI21_X2)
   0.04    0.60 ^ _17224_/ZN (AOI21_X1)
   0.02    0.61 v _17225_/ZN (NOR2_X1)
   0.02    0.64 ^ _17228_/ZN (NAND2_X1)
   0.02    0.66 v _17234_/ZN (NAND3_X1)
   0.03    0.69 ^ _17235_/ZN (OAI21_X1)
   0.03    0.72 v _17239_/ZN (OAI21_X2)
   0.04    0.76 ^ _17245_/ZN (AOI21_X2)
   0.02    0.79 v _17249_/ZN (OAI21_X2)
   0.06    0.84 ^ _17255_/ZN (OAI21_X1)
   0.03    0.87 v _17259_/ZN (OAI21_X2)
   0.04    0.91 ^ _17264_/ZN (AOI21_X1)
   0.03    0.95 ^ _17265_/ZN (OR2_X2)
   0.02    0.96 v _17269_/ZN (OAI21_X2)
   0.06    1.02 ^ _17275_/ZN (OAI21_X1)
   0.03    1.05 v _17279_/ZN (OAI21_X2)
   0.04    1.09 ^ _17285_/ZN (OAI21_X2)
   0.02    1.11 v _17289_/ZN (OAI21_X2)
   0.06    1.17 ^ _17295_/ZN (OAI21_X1)
   0.03    1.20 v _17299_/ZN (OAI21_X2)
   0.02    1.22 ^ _17304_/ZN (OAI21_X1)
   0.04    1.26 ^ _17305_/ZN (AND2_X2)
   0.02    1.28 v _17309_/ZN (OAI21_X2)
   0.04    1.31 v _17311_/ZN (XNOR2_X1)
   0.00    1.31 v _21813_/D (DFF_X1)
           1.31   data arrival time

   1.00    1.00   clock core_clock (rise edge)
   0.00    1.00   clock network delay (ideal)
   0.00    1.00   clock reconvergence pessimism
           1.00 ^ _21813_/CK (DFF_X1)
  -0.04    0.96   library setup time
           0.96   data required time
---------------------------------------------------------
           0.96   data required time
          -1.31   data arrival time
---------------------------------------------------------
          -0.35   slack (VIOLATED)



==========================================================================
report_tns
--------------------------------------------------------------------------
tns -71.14

==========================================================================
report_wns
--------------------------------------------------------------------------
wns -0.35

==========================================================================
report_design_area
--------------------------------------------------------------------------
Design area 20108 u^2 3% utilization.
0:07.03elapsed 100%CPU 87376memKB
(/usr/bin/time -f "%Eelapsed %PCPU %MmemKB" openroad -no_init -exit ./scripts/io_placement.tcl) 2>&1 | tee ./logs/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/2_2_floorplan_io.log
OpenROAD 1.1.0 ef1118f201
License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0:     Created 22 technology layers
Notice 0:     Created 27 technology vias
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0:     Created 134 library cells
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0: 
Reading DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/2_1_floorplan.def
Notice 0: Design: _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
Notice 0:     Created 1173 pins.
Notice 0:     Created 11967 components and 65389 component-terminals.
Notice 0:     Created 14573 nets and 41455 connections.
Notice 0: Finished DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/2_1_floorplan.def
WARNING: force pin spread option has no effect when using random pin placement
 > Running IO placement
 * Num of slots          21102
 * Num of I/O            1173
 * Num of I/O w/sink     1130
 * Num of I/O w/o sink   43
 * Slots Per Section     200
 * Slots Increase Factor 0.01
 * Usage Per Section     0.8
 * Usage Increase Factor 0.01
 * Force Pin Spread      1

WARNING: running random pin placement
RandomMode Even
 > IO placement done.
0:01.67elapsed 99%CPU 71716memKB
(/usr/bin/time -f "%Eelapsed %PCPU %MmemKB" openroad -no_init -exit ./scripts/tdms_place.tcl) 2>&1 | tee ./logs/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/2_3_tdms_place.log
OpenROAD 1.1.0 ef1118f201
License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0:     Created 22 technology layers
Notice 0:     Created 27 technology vias
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0:     Created 134 library cells
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0: 
Reading DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/2_2_floorplan_io.def
Notice 0: Design: _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
Notice 0:     Created 1173 pins.
Notice 0:     Created 11967 components and 65389 component-terminals.
Notice 0:     Created 14573 nets and 41455 connections.
Notice 0: Finished DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/2_2_floorplan_io.def
No macros found: Skipping global_placement
0:01.68elapsed 99%CPU 76744memKB
./util/fixIoPins.py --inputDef results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/2_3_floorplan_tdms.def --outputDef results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/2_3_floorplan_tdms.def --margin 70
fixIoPins.py : Fixing Pins in Def file
Replacements made - West:337 South:249 East:338 North:249
fixIoPins.py : Finished
(/usr/bin/time -f "%Eelapsed %PCPU %MmemKB" openroad -no_init -exit ./scripts/macro_place.tcl) 2>&1 | tee ./logs/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/2_4_mplace.log
OpenROAD 1.1.0 ef1118f201
License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0:     Created 22 technology layers
Notice 0:     Created 27 technology vias
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0:     Created 134 library cells
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0: 
Reading DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/2_3_floorplan_tdms.def
Notice 0: Design: _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
Notice 0:     Created 1173 pins.
Notice 0:     Created 11967 components and 65389 component-terminals.
Notice 0:     Created 14573 nets and 41455 connections.
Notice 0: Finished DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/2_3_floorplan_tdms.def
No macros found: Skipping macro_placement
0:01.71elapsed 99%CPU 76880memKB
(/usr/bin/time -f "%Eelapsed %PCPU %MmemKB" openroad -no_init -exit ./scripts/tapcell.tcl) 2>&1 | tee ./logs/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/2_5_tapcell.log
OpenROAD 1.1.0 ef1118f201
License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0:     Created 22 technology layers
Notice 0:     Created 27 technology vias
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0:     Created 134 library cells
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0: 
Reading DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/2_4_floorplan_macro.def
Notice 0: Design: _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
Notice 0:     Created 1173 pins.
Notice 0:     Created 11967 components and 65389 component-terminals.
Notice 0:     Created 14573 nets and 41455 connections.
Notice 0: Finished DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/2_4_floorplan_macro.def
Running tapcell...
Step 1: Cut rows...
[INFO] Macro blocks found: 0
[INFO] #Original rows: 592
[INFO] #Cut rows: 0
Step 2: Insert endcaps...
[INFO]#Endcaps inserted: 1184
Step 3: Insert tapcells...
[INFO] #Tapcells inserted: 1782
Running tapcell... Done!
0:03.05elapsed 99%CPU 85532memKB
(/usr/bin/time -f "%Eelapsed %PCPU %MmemKB" openroad -no_init -exit ./scripts/pdn.tcl) 2>&1 | tee ./logs/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/2_6_pdn.log
OpenROAD 1.1.0 ef1118f201
License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0:     Created 22 technology layers
Notice 0:     Created 27 technology vias
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0:     Created 134 library cells
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0: 
Reading DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/2_5_floorplan_tapcell.def
Notice 0: Design: _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
Notice 0:     Created 1173 pins.
Notice 0:     Created 14933 components and 71321 component-terminals.
Notice 0:     Created 14573 nets and 41455 connections.
Notice 0: Finished DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/2_5_floorplan_tapcell.def
[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN
[INFO] [PDNG-0016]   config: ./platforms/nangate45/pdn.cfg
[INFO] [PDNG-0008] Design Name is _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
[INFO] [PDNG-0009] Reading technology data
[INFO] [PDNG-0011] ****** INFO ******
Type: stdcell, grid
    Stdcell Rails
      Layer: metal1 -  width: 0.170  pitch: 2.400  offset: 0.000 
    Straps
      Layer: metal4 -  width: 0.480  pitch: 56.000  offset: 2.000 
      Layer: metal7 -  width: 1.400  pitch: 40.000  offset: 2.000 
    Connect: {metal1 metal4} {metal4 metal7}
Type: macro, macro_1
    Macro orientation: R0 R180 MX MY
    Straps
      Layer: metal5 -  width: 0.930  pitch: 10.000  offset: 2.000 
      Layer: metal6 -  width: 0.930  pitch: 10.000  offset: 2.000 
    Connect: {metal4_PIN_ver metal5} {metal5 metal6} {metal6 metal7}
Type: macro, macro_2
    Macro orientation: R90 R270 MXR90 MYR90
    Straps
      Layer: metal6 -  width: 0.930  pitch: 40.000  offset: 2.000 
    Connect: {metal4_PIN_hor metal6} {metal6 metal7}
[INFO] [PDNG-0012] **** END INFO ****
[INFO] [PDNG-0013] Inserting stdcell grid - grid
[INFO] [PDNG-0015] Writing to database
0:04.41elapsed 99%CPU 214516memKB
cp results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/2_6_floorplan_pdn.def results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/2_floorplan.def
(/usr/bin/time -f "%Eelapsed %PCPU %MmemKB" openroad -no_init -exit ./scripts/global_place.tcl) 2>&1 | tee ./logs/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/3_1_place_gp.log
OpenROAD 1.1.0 ef1118f201
License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0:     Created 22 technology layers
Notice 0:     Created 27 technology vias
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0:     Created 134 library cells
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0: 
Reading DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/2_floorplan.def
Notice 0: Design: _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
Notice 0:     Created 1173 pins.
Notice 0:     Created 14933 components and 71321 component-terminals.
Notice 0:     Created 2 special nets and 29866 connections.
Notice 0:     Created 14573 nets and 41455 connections.
Notice 0: Finished DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/2_floorplan.def
[INFO] DBU = 2000
[INFO] SiteSize = (380, 2800)
[INFO] CoreAreaLxLy = (20140, 22400)
[INFO] CoreAreaUxUy = (1680360, 1680000)
[INFO] NumInstances = 14933
[INFO] NumPlaceInstances = 11967
[INFO] NumFixedInstances = 2966
[INFO] NumDummyInstances = 0
[INFO] NumNets = 14573
[INFO] NumPins = 42628
[INFO] DieAreaLxLy = (0, 0)
[INFO] DieAreaUxUy = (1700260, 1701600)
[INFO] CoreAreaLxLy = (20140, 22400)
[INFO] CoreAreaUxUy = (1680360, 1680000)
[INFO] CoreArea = 2751980672000
[INFO] NonPlaceInstsArea = 3155824000
[INFO] PlaceInstsArea = 131363568000
[INFO] Util(%) = 4.778899
[INFO] StdInstsArea = 131363568000
[INFO] MacroInstsArea = 0
[InitialPlace]  Iter: 1 CG Error: 0.000100334 HPWL: 2022488920
[InitialPlace]  Iter: 2 CG Error: 0.000139521 HPWL: 1537499160
[InitialPlace]  Iter: 3 CG Error: 6.49797e-05 HPWL: 1514822679
[InitialPlace]  Iter: 4 CG Error: 2.07069e-05 HPWL: 1501081972
[InitialPlace]  Iter: 5 CG Error: 1.10423e-06 HPWL: 1498972802
[INFO] FillerInit: NumGCells = 77591
[INFO] FillerInit: NumGNets = 14573
[INFO] FillerInit: NumGPins = 42628
[INFO] TargetDensity = 0.300000
[INFO] AveragePlaceInstArea = 10977151
[INFO] IdealBinArea = 36590500
[INFO] IdealBinCnt = 75210
[INFO] TotalBinArea = 2751980672000
[INFO] BinCnt = (256, 256)
[INFO] BinSize = (6486, 6475)
[INFO] NumBins = 65536
[NesterovSolve] Iter: 1 overflow: 0.931238 HPWL: 1706882374
[NesterovSolve] Iter: 10 overflow: 0.812751 HPWL: 1737430256
[NesterovSolve] Iter: 20 overflow: 0.799369 HPWL: 1720221021
[NesterovSolve] Iter: 30 overflow: 0.796443 HPWL: 1718354683
[NesterovSolve] Iter: 40 overflow: 0.796511 HPWL: 1717269197
[NesterovSolve] Iter: 50 overflow: 0.796285 HPWL: 1717615191
[NesterovSolve] Iter: 60 overflow: 0.796683 HPWL: 1717782650
[NesterovSolve] Iter: 70 overflow: 0.796748 HPWL: 1717561877
[NesterovSolve] Iter: 80 overflow: 0.797027 HPWL: 1717561206
[NesterovSolve] Iter: 90 overflow: 0.796839 HPWL: 1717485089
[NesterovSolve] Iter: 100 overflow: 0.79666 HPWL: 1717648707
[NesterovSolve] Iter: 110 overflow: 0.796461 HPWL: 1717866988
[NesterovSolve] Iter: 120 overflow: 0.796226 HPWL: 1718050434
[NesterovSolve] Iter: 130 overflow: 0.795838 HPWL: 1718435821
[NesterovSolve] Iter: 140 overflow: 0.7952 HPWL: 1718991393
[NesterovSolve] Iter: 150 overflow: 0.794196 HPWL: 1720010754
[NesterovSolve] Iter: 160 overflow: 0.792409 HPWL: 1721697244
[NesterovSolve] Iter: 170 overflow: 0.789482 HPWL: 1725686156
[NesterovSolve] Iter: 180 overflow: 0.785397 HPWL: 1732671171
[NesterovSolve] Iter: 190 overflow: 0.778423 HPWL: 1738846670
[NesterovSolve] Iter: 200 overflow: 0.76695 HPWL: 1741887798
[NesterovSolve] Iter: 210 overflow: 0.751864 HPWL: 1738894216
[NesterovSolve] Iter: 220 overflow: 0.72797 HPWL: 1736694632
[NesterovSolve] Iter: 230 overflow: 0.697332 HPWL: 1747097217
[NesterovSolve] Iter: 240 overflow: 0.659341 HPWL: 1747762923
[NesterovSolve] Iter: 250 overflow: 0.622562 HPWL: 1756171908
[NesterovSolve] Iter: 260 overflow: 0.575861 HPWL: 1768060851
[NesterovSolve] Iter: 270 overflow: 0.530657 HPWL: 1782592772
[NesterovSolve] Iter: 280 overflow: 0.498348 HPWL: 1787622273
[NesterovSolve] Iter: 290 overflow: 0.457615 HPWL: 1801502386
[NesterovSolve] Iter: 300 overflow: 0.419398 HPWL: 1806246477
[NesterovSolve] Iter: 310 overflow: 0.385812 HPWL: 1808845744
[NesterovSolve] Iter: 320 overflow: 0.352467 HPWL: 1815729862
[NesterovSolve] Iter: 330 overflow: 0.321249 HPWL: 1816966951
[NesterovSolve] Iter: 340 overflow: 0.291189 HPWL: 1819104244
[NesterovSolve] Iter: 350 overflow: 0.261277 HPWL: 1821137388
[NesterovSolve] Iter: 360 overflow: 0.233592 HPWL: 1823344995
[NesterovSolve] Iter: 370 overflow: 0.209445 HPWL: 1825168674
[NesterovSolve] Iter: 380 overflow: 0.184938 HPWL: 1826947881
[NesterovSolve] Iter: 390 overflow: 0.164151 HPWL: 1828545675
[NesterovSolve] Iter: 400 overflow: 0.1454 HPWL: 1829962703
[NesterovSolve] Iter: 410 overflow: 0.129408 HPWL: 1831631518
[NesterovSolve] Iter: 420 overflow: 0.114807 HPWL: 1832998826
[NesterovSolve] Iter: 430 overflow: 0.101463 HPWL: 1827749598
[NesterovSolve] Finished with Overflow: 0.099852
1:34.69elapsed 99%CPU 161996memKB
(/usr/bin/time -f "%Eelapsed %PCPU %MmemKB" openroad -no_init -exit ./scripts/resize.tcl) 2>&1 | tee ./logs/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/3_2_resizer.log
OpenROAD 1.1.0 ef1118f201
License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0:     Created 22 technology layers
Notice 0:     Created 27 technology vias
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0:     Created 134 library cells
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0: 
Reading DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/3_1_place_gp.def
Notice 0: Design: _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
Notice 0:     Created 1173 pins.
Notice 0:     Created 14933 components and 71321 component-terminals.
Notice 0:     Created 2 special nets and 29866 connections.
Notice 0:     Created 14573 nets and 41455 connections.
Notice 0: Finished DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/3_1_place_gp.def

==========================================================================
report_checks
--------------------------------------------------------------------------
Startpoint: _21751_ (rising edge-triggered flip-flop clocked by core_clock)
Endpoint: _21813_ (rising edge-triggered flip-flop clocked by core_clock)
Path Group: core_clock
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock core_clock (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 ^ _21751_/CK (DFF_X1)
   0.08    0.08 v _21751_/Q (DFF_X1)
   0.03    0.11 v _12699_/Z (BUF_X4)
   0.02    0.13 ^ _17174_/ZN (NOR2_X2)
   0.02    0.15 v _17175_/ZN (OAI21_X2)
   0.11    0.25 ^ _17185_/ZN (AOI221_X1)
   0.02    0.27 v _17189_/ZN (NOR3_X2)
   0.03    0.31 ^ _17191_/ZN (OAI21_X2)
   0.02    0.32 v _17196_/ZN (AOI21_X2)
   0.06    0.38 ^ _17199_/ZN (AOI21_X1)
   0.02    0.41 v _17205_/ZN (AOI21_X2)
   0.02    0.43 ^ _17208_/ZN (NAND2_X2)
   0.01    0.44 v _17214_/ZN (AOI21_X2)
   0.06    0.50 ^ _17215_/ZN (AOI21_X1)
   0.03    0.53 v _17219_/ZN (OAI21_X2)
   0.04    0.57 ^ _17224_/ZN (AOI21_X1)
   0.02    0.58 v _17225_/ZN (NOR2_X1)
   0.02    0.61 ^ _17228_/ZN (NAND2_X1)
   0.02    0.63 v _17234_/ZN (NAND3_X1)
   0.03    0.66 ^ _17235_/ZN (OAI21_X1)
   0.03    0.68 v _17239_/ZN (OAI21_X2)
   0.04    0.72 ^ _17245_/ZN (AOI21_X2)
   0.02    0.74 v _17249_/ZN (OAI21_X2)
   0.05    0.80 ^ _17255_/ZN (OAI21_X1)
   0.02    0.82 v _17259_/ZN (OAI21_X2)
   0.04    0.87 ^ _17264_/ZN (AOI21_X1)
   0.03    0.90 ^ _17265_/ZN (OR2_X2)
   0.02    0.91 v _17269_/ZN (OAI21_X2)
   0.05    0.97 ^ _17275_/ZN (OAI21_X1)
   0.03    0.99 v _17279_/ZN (OAI21_X2)
   0.04    1.03 ^ _17285_/ZN (OAI21_X2)
   0.02    1.06 v _17289_/ZN (OAI21_X2)
   0.05    1.11 ^ _17295_/ZN (OAI21_X1)
   0.02    1.13 v _17299_/ZN (OAI21_X2)
   0.02    1.16 ^ _17304_/ZN (OAI21_X1)
   0.04    1.19 ^ _17305_/ZN (AND2_X2)
   0.02    1.21 v _17309_/ZN (OAI21_X2)
   0.04    1.24 v _17311_/ZN (XNOR2_X1)
   0.00    1.24 v _21813_/D (DFF_X1)
           1.24   data arrival time

   1.00    1.00   clock core_clock (rise edge)
   0.00    1.00   clock network delay (ideal)
   0.00    1.00   clock reconvergence pessimism
           1.00 ^ _21813_/CK (DFF_X1)
  -0.04    0.96   library setup time
           0.96   data required time
---------------------------------------------------------
           0.96   data required time
          -1.24   data arrival time
---------------------------------------------------------
          -0.29   slack (VIOLATED)



==========================================================================
report_tns
--------------------------------------------------------------------------
tns -35.40

==========================================================================
report_wns
--------------------------------------------------------------------------
wns -0.29

==========================================================================
report_design_area
--------------------------------------------------------------------------
Design area 20897 u^2 3% utilization.

==========================================================================
instance_count
--------------------------------------------------------------------------
14933

==========================================================================
pin_count
--------------------------------------------------------------------------
41455

Perform port buffering...
Inserted 1091 input buffers.
Inserted 81 output buffers.
Repair max cap...
Repair max slew...
Repair max fanout...
Perform resizing...
Warning: resize.tcl, 79 resize -dont_use is deprecated. Use the set_dont_use commands instead.
Resized 2673 instances.
Repair tie lo fanout...
Repair tie hi fanout...
Repair hold violations...
Inserted 0 hold buffers.

==========================================================================
report_floating_nets
--------------------------------------------------------------------------
Warning: found 1511 floatiing nets.

==========================================================================
report_checks
--------------------------------------------------------------------------
Startpoint: _22362_ (rising edge-triggered flip-flop clocked by core_clock)
Endpoint: _22870_ (rising edge-triggered flip-flop clocked by core_clock)
Path Group: core_clock
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock core_clock (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 ^ _22362_/CK (DFF_X1)
   0.09    0.09 v _22362_/Q (DFF_X1)
   0.04    0.12 v _14368_/ZN (XNOR2_X2)
   0.04    0.16 ^ _14395_/ZN (OAI21_X2)
   0.03    0.19 v _14462_/ZN (AOI221_X2)
   0.06    0.25 ^ _14493_/ZN (NOR3_X1)
   0.02    0.27 v _14495_/ZN (OAI21_X1)
   0.04    0.31 v _14550_/ZN (AND2_X1)
   0.04    0.35 ^ _14603_/ZN (OAI21_X1)
   0.02    0.36 v _14643_/ZN (AOI21_X1)
   0.06    0.42 v _14644_/ZN (OR2_X1)
   0.04    0.46 ^ _14662_/ZN (OAI21_X1)
   0.02    0.49 v _14703_/ZN (AOI21_X1)
   0.04    0.53 ^ _14721_/ZN (OAI21_X1)
   0.02    0.55 v _14768_/ZN (AOI21_X1)
   0.06    0.60 v _14769_/ZN (OR2_X1)
   0.04    0.65 ^ _14819_/ZN (OAI21_X1)
   0.02    0.66 v _14834_/ZN (AOI21_X1)
   0.04    0.71 ^ _14835_/ZN (NOR2_X1)
   0.02    0.73 v _14885_/ZN (AOI21_X1)
   0.06    0.79 ^ _14914_/ZN (OAI21_X1)
   0.03    0.82 v _14985_/ZN (NAND3_X1)
   0.04    0.86 ^ _15007_/ZN (NOR2_X1)
   0.05    0.90 ^ _15009_/ZN (AND2_X1)
   0.06    0.97 ^ _15072_/ZN (AND3_X1)
   0.03    1.00 v _15124_/ZN (NAND3_X1)
   0.05    1.05 ^ _15186_/ZN (NOR2_X1)
   0.03    1.09 v _15249_/ZN (NAND3_X1)
   0.06    1.15 ^ _15279_/ZN (NOR2_X1)
   0.05    1.19 ^ _15280_/ZN (XNOR2_X1)
   0.02    1.21 v _15281_/ZN (AOI21_X1)
   0.04    1.25 ^ _15283_/ZN (AOI21_X1)
   0.02    1.27 v _15284_/ZN (OAI21_X1)
   0.04    1.31 ^ _15290_/ZN (AOI21_X1)
   0.01    1.32 v _15291_/ZN (NOR3_X1)
   0.04    1.36 ^ _15292_/ZN (AOI21_X1)
   0.01    1.37 v _15293_/ZN (INV_X1)
   0.00    1.37 v _22870_/D (DFF_X1)
           1.37   data arrival time

   1.00    1.00   clock core_clock (rise edge)
   0.00    1.00   clock network delay (ideal)
   0.00    1.00   clock reconvergence pessimism
           1.00 ^ _22870_/CK (DFF_X1)
  -0.04    0.96   library setup time
           0.96   data required time
---------------------------------------------------------
           0.96   data required time
          -1.37   data arrival time
---------------------------------------------------------
          -0.41   slack (VIOLATED)



==========================================================================
report_tns
--------------------------------------------------------------------------
tns -54.91

==========================================================================
report_wns
--------------------------------------------------------------------------
wns -0.41

==========================================================================
report_design_area
--------------------------------------------------------------------------
Design area 21436 u^2 3% utilization.

==========================================================================
instance_count
--------------------------------------------------------------------------
16105

==========================================================================
pin_count
--------------------------------------------------------------------------
43799

0:21.54elapsed 100%CPU 135696memKB
(/usr/bin/time -f "%Eelapsed %PCPU %MmemKB" openroad -no_init -exit ./scripts/detail_place.tcl) 2>&1 | tee ./logs/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/3_3_opendp.log
OpenROAD 1.1.0 ef1118f201
License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0:     Created 22 technology layers
Notice 0:     Created 27 technology vias
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0:     Created 134 library cells
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0: 
Reading DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/3_2_place_resized.def
Notice 0: Design: _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
Notice 0:     Created 1173 pins.
Notice 0:     Created 16105 components and 76009 component-terminals.
Notice 0:     Created 2 special nets and 32210 connections.
Notice 0:     Created 15745 nets and 43799 connections.
Notice 0: Finished DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/3_2_place_resized.def
Design Stats
--------------------------------
total instances         16105
multi row instances         0
fixed instances          2966
nets                    15747
design area          687995.2 u^2
fixed area              789.0 u^2
movable area          20646.9 u^2
utilization                 3 %
utilization padded          4 %
rows                      592
row height                1.4 u

Placement Analysis
--------------------------------
total displacement    12857.1 u
average displacement      0.8 u
max displacement          6.6 u
original HPWL        919572.4 u
legalized HPWL       924146.0 u
delta HPWL                  0 %

0:02.62elapsed 99%CPU 197260memKB
cp results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/3_3_place_dp.def results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/3_place.def
cp results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/2_floorplan.sdc results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/3_place.sdc
(/usr/bin/time -f "%Eelapsed %PCPU %MmemKB" openroad -no_init -exit ./scripts/cts.tcl) 2>&1 | tee ./logs/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/4_1_cts.log
OpenROAD 1.1.0 ef1118f201
License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0:     Created 22 technology layers
Notice 0:     Created 27 technology vias
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0:     Created 134 library cells
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0: 
Reading DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/3_place.def
Notice 0: Design: _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
Notice 0:     Created 1173 pins.
Notice 0:     Created 16105 components and 76009 component-terminals.
Notice 0:     Created 2 special nets and 32210 connections.
Notice 0:     Created 15745 nets and 43799 connections.
Notice 0: Finished DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/3_place.def

==========================================================================
report_checks
--------------------------------------------------------------------------
Startpoint: _22362_ (rising edge-triggered flip-flop clocked by core_clock)
Endpoint: _22870_ (rising edge-triggered flip-flop clocked by core_clock)
Path Group: core_clock
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock core_clock (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 ^ _22362_/CK (DFF_X1)
   0.09    0.09 v _22362_/Q (DFF_X1)
   0.04    0.13 v _14368_/ZN (XNOR2_X2)
   0.04    0.17 ^ _14395_/ZN (OAI21_X2)
   0.03    0.20 v _14462_/ZN (AOI221_X2)
   0.07    0.26 ^ _14493_/ZN (NOR3_X1)
   0.02    0.29 v _14495_/ZN (OAI21_X1)
   0.04    0.32 v _14550_/ZN (AND2_X1)
   0.05    0.37 ^ _14603_/ZN (OAI21_X1)
   0.02    0.39 v _14643_/ZN (AOI21_X1)
   0.06    0.44 v _14644_/ZN (OR2_X1)
   0.05    0.49 ^ _14662_/ZN (OAI21_X1)
   0.03    0.52 v _14703_/ZN (AOI21_X1)
   0.05    0.57 ^ _14721_/ZN (OAI21_X1)
   0.02    0.58 v _14768_/ZN (AOI21_X1)
   0.06    0.64 v _14769_/ZN (OR2_X1)
   0.05    0.69 ^ _14819_/ZN (OAI21_X1)
   0.02    0.71 v _14834_/ZN (AOI21_X1)
   0.05    0.75 ^ _14835_/ZN (NOR2_X1)
   0.03    0.78 v _14885_/ZN (AOI21_X1)
   0.06    0.84 ^ _14914_/ZN (OAI21_X1)
   0.04    0.88 v _14985_/ZN (NAND3_X1)
   0.04    0.92 ^ _15007_/ZN (NOR2_X1)
   0.05    0.97 ^ _15009_/ZN (AND2_X1)
   0.07    1.04 ^ _15072_/ZN (AND3_X1)
   0.04    1.08 v _15124_/ZN (NAND3_X1)
   0.06    1.14 ^ _15186_/ZN (NOR2_X1)
   0.04    1.17 v _15249_/ZN (NAND3_X1)
   0.07    1.24 ^ _15279_/ZN (NOR2_X1)
   0.05    1.29 ^ _15280_/ZN (XNOR2_X1)
   0.02    1.31 v _15281_/ZN (AOI21_X1)
   0.04    1.35 ^ _15283_/ZN (AOI21_X1)
   0.02    1.37 v _15284_/ZN (OAI21_X1)
   0.04    1.41 ^ _15290_/ZN (AOI21_X1)
   0.01    1.42 v _15291_/ZN (NOR3_X1)
   0.04    1.47 ^ _15292_/ZN (AOI21_X1)
   0.01    1.47 v _15293_/ZN (INV_X1)
   0.00    1.47 v _22870_/D (DFF_X1)
           1.47   data arrival time

   1.00    1.00   clock core_clock (rise edge)
   0.00    1.00   clock network delay (ideal)
   0.00    1.00   clock reconvergence pessimism
           1.00 ^ _22870_/CK (DFF_X1)
  -0.04    0.96   library setup time
           0.96   data required time
---------------------------------------------------------
           0.96   data required time
          -1.47   data arrival time
---------------------------------------------------------
          -0.51   slack (VIOLATED)


 *****************
 * TritonCTS 2.0 *
 *****************
 *****************************
 *  Import characterization  *
 *****************************
 Reading LUT file "./platforms/nangate45/tritonCTS/lut.txt"
    Min. len    Max. len    Min. cap    Max. cap   Min. slew   Max. slew
           2           8           1          52           1          24
    [WARNING] 180 wires are pure wire and no slew degration.
    TritonCTS forced slew degradation on these wires.
    Num wire segments: 4994
    Num keys in characterization LUT: 1677
    Actual min input cap: 8
 Reading solution list file "./platforms/nangate45/tritonCTS/sol_list.txt"
 **********************
 *  Find clock roots  *
 **********************
 User did not specify clock roots.
 Using OpenSTA to find clock roots.
 Looking for clock sources...
    Clock names: clock 
 ************************
 *  Populate TritonCTS  *
 ************************
 Initializing clock nets
 Number of user-input clocks: 1 ( "clock" )
 Looking for clock nets in the design
 Net "clock" found
clock
 ****************************
 *  Check characterization  *
 ****************************
    The chacterization used 1 buffer(s) types. All of them are in the loaded DB.
 ***********************
 *  Build clock trees  *
 ***********************
 Generating H-Tree topology for net clock...
    Tot. number of sinks: 1514
 Wire segment unit: 20000 dbu (10 um)
 Original sink region: [(467210, 524830), (1219230, 1205570)]
 Normalized sink region: [(23.3605, 26.2415), (60.9615, 60.2785)]
    Width:  37.601
    Height: 34.037
 Level 1
    Direction: Horizontal
    # sinks per sub-region: 757
    Sub-region size: 18.8005 X 34.037
    Segment length (rounded): 10
    Key: 3192 outSlew: 1 load: 1 length: 8 isBuffered: 1
    Key: 0 outSlew: 2 load: 1 length: 2 isBuffered: 0
 Level 2
    Direction: Vertical
    # sinks per sub-region: 379
    Sub-region size: 18.8005 X 17.0185
    Segment length (rounded): 8
    Key: 3206 outSlew: 1 load: 1 length: 8 isBuffered: 1
 Level 3
    Direction: Horizontal
    # sinks per sub-region: 190
    Sub-region size: 9.40025 X 17.0185
    Segment length (rounded): 4
    Key: 1170 outSlew: 12 load: 1 length: 4 isBuffered: 1
 Level 4
    Direction: Vertical
    # sinks per sub-region: 95
    Sub-region size: 9.40025 X 8.50925
    Segment length (rounded): 4
    Key: 1242 outSlew: 12 load: 1 length: 4 isBuffered: 1
 Level 5
    Direction: Horizontal
    # sinks per sub-region: 48
    Sub-region size: 4.70012 X 8.50925
    Segment length (rounded): 2
    Key: 548 outSlew: 2 load: 1 length: 2 isBuffered: 1
 Level 6
    Direction: Vertical
    # sinks per sub-region: 24
    Sub-region size: 4.70012 X 4.25462
    Segment length (rounded): 2
    Key: 0 outSlew: 2 load: 1 length: 2 isBuffered: 0
 [WARNING] Creating fake entries in the LUT.
 Level 7
    Direction: Horizontal
    # sinks per sub-region: 12
    Sub-region size: 2.35006 X 4.25462
    Segment length (rounded): 1
    Key: 5030 outSlew: 12 load: 1 length: 1 isBuffered: 1
 Stop criterion found. Max number of sinks is (15)
 Building clock sub nets...
 Number of sinks covered: 1514
 Clock topology of net "clock" done.
 ****************
 * Post CTS opt *
 ****************
 Avg. source sink dist: 41899.5 dbu.
 Num outlier sinks: 5
 ********************
 * Write data to DB *
 ********************
 Writing clock net "clock" to DB
    Created 196 clock buffers.
    Created 196 clock nets.
 ... End of TritonCTS execution.
Design Stats
--------------------------------
total instances         16301
multi row instances         0
fixed instances          2966
nets                    15943
design area          687995.2 u^2
fixed area              789.0 u^2
movable area          20809.7 u^2
utilization                 3 %
utilization padded          4 %
rows                      592
row height                1.4 u

Placement Analysis
--------------------------------
total displacement      171.7 u
average displacement      0.0 u
max displacement          2.8 u
original HPWL        935639.3 u
legalized HPWL       935647.4 u
delta HPWL                  0 %

0:08.61elapsed 100%CPU 209404memKB
(/usr/bin/time -f "%Eelapsed %PCPU %MmemKB" openroad -no_init -exit ./scripts/fillcell.tcl) 2>&1 | tee ./logs/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/4_2_cts_fillcell.log
OpenROAD 1.1.0 ef1118f201
License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0:     Created 22 technology layers
Notice 0:     Created 27 technology vias
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0:     Created 134 library cells
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0: 
Reading DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/4_1_cts.def
Notice 0: Design: _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
Notice 0:     Created 1173 pins.
Notice 0:     Created 16301 components and 76793 component-terminals.
Notice 0:     Created 2 special nets and 32602 connections.
Notice 0:     Created 15941 nets and 44191 connections.
Notice 0: Finished DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/4_1_cts.def
Placed 118929 filler instances.
0:03.17elapsed 99%CPU 337432memKB
cp results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/4_2_cts_fillcell.def results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/4_cts.def
(/usr/bin/time -f "%Eelapsed %PCPU %MmemKB" openroad -no_init -exit ./scripts/global_route.tcl) 2>&1 | tee ./logs/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/5_1_fastroute.log
OpenROAD 1.1.0 ef1118f201
License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>

This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details. 
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0:     Created 22 technology layers
Notice 0:     Created 27 technology vias
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.tech.lef
Notice 0: Reading LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0:     Created 134 library cells
Notice 0: Finished LEF file:  ./platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
Notice 0: 
Reading DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/4_cts.def
Notice 0: Design: _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
Notice 0: 		Created 100000 Insts
Notice 0:     Created 1173 pins.
Notice 0:     Created 135230 components and 314651 component-terminals.
Notice 0:     Created 2 special nets and 270460 connections.
Notice 0:     Created 15941 nets and 44191 connections.
Notice 0: Finished DEF file: ./results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/4_cts.def

 *****************
 *   FastRoute   *
 *****************

[PARAMS] Min routing layer: 2
[PARAMS] Max routing layer: 10
[PARAMS] Global adjustment: 0.15
[PARAMS] Unidirectional routing: 1
[PARAMS] Clock net routing: 0
[PARAMS] Grid origin: (-1, -1)
Initializing grid...
[INFO] #DB Obstructions: 0
[INFO] #DB Obstacles: 91449
[INFO] #DB Macros: 0
Initializing grid... Done!
Searching for transition layers...
[INFO] Found 0 transition layers
Searching for transition layers... Done!
Initializing routing layers...
Initializing routing layers... Done!
Initializing routing tracks...
Initializing routing tracks... Done!
Setting capacities...
Setting capacities... Done!
Setting spacings and widths...
Setting spacings and widths... Done!
Initializing nets...
Checking pin placement...
Checking pin placement... Done!
Initializing nets... Done!
Adjusting grid...
Adjusting grid... Done!
Computing track adjustments...
Computing track adjustments... Done!
Computing obstacles adjustments...
[INFO] Processing 488762 obstacles in layer 1
[INFO] Processing 30 obstacles in layer 4
[INFO] Processing 42 obstacles in layer 7
Computing obstacles adjustments... Done!
Computing user defined adjustments...
Computing user defined adjustments... Done!
Computing user defined layers adjustments...
[INFO] Reducing resources of layer 2 in 50%
[INFO] Reducing resources of layer 3 in 50%
Computing user defined layers adjustments... Done!
[INFO] Elapsed time: 1.92481
Running FastRoute...


Final usage/overflow report: 

[Overflow Report] Total Usage   : 456462
[Overflow Report] Total Capacity: 4390909
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow  : 0
[Overflow Report] H   Overflow  : 0
[Overflow Report] V   Overflow  : 0
[Overflow Report] Final Overflow: 0

[INFO] Final usage          : 456462
[INFO] Final number of vias : 80252
[INFO] Final usage 3D       : 697218
Getting results...
Getting results... Done!

Running FastRoute... Done!
[INFO] Total wirelength: 1917140.375000 um
[INFO] Elapsed time: 5.391794
Writing guides...
[INFO] Num routed nets: 15662
[ERROR] Net __Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy_i0.Datapath_i.fu__Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy_419510_419627.out1\[10\]�+ has segments vector empty
Command exited with non-zero status 1
0:16.97elapsed 99%CPU 414492memKB
Makefile:326: recipe for target 'results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/route.guide' failed
make: *** [results/nangate45/_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy/route.guide] Error 1

opendp combination issue of padding and filler insertion

If filler insertion is performed after detailed placement with padding, the empty space of DEF due to padding will not be filled.
The padded cells should eventually be returned to their original size, so I think the filler should be filled between the cells.

I tested it by adding functions based on low_util01.tcl.

read_lef Nangate45.lef
read_def nangate45-bench/gcd/gcd_replace.def
set_placement_padding -global -left 20 -right 20
detailed_placement
filler_placement FILL*
check_placement

set def_file [make_result_file low_util01.def]
write_def $def_file
diff_file $def_file low_util01.defok

Below is the test result figure.
padding_filler

Thanks,

OpenROAD is crashing while starting FastRoute

OpenROAD is crashing while starting FastRoute for https://github.com/tamimcse/test/blob/master/top.v. The Verilog is generated using Bambu HLS. The OpenROAD script is https://github.com/tamimcse/test/blob/master/bash_script.sh. The output is as following: You will see the crash at the very end.

`.....
......
yosys> opt_clean -purge

Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy..
Removed 96 unused cells and 9494 unused wires.
<suppressed ~183 debug messages>
y_typical.lib iberty /opt/panda/share/panda//nangate45/lib/NangateOpenCellLibrary

Printing statistics.
=== _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy ===

Number of wires: 20066
Number of wire bits: 21196
Number of public wires: 2469
Number of public wire bits: 3599
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 18580
AND2_X1 1925
AND2_X2 49
AND2_X4 45
AND3_X1 488
AND3_X2 3
AND3_X4 6
AND4_X1 120
AND4_X2 3
AND4_X4 3
AOI211_X1 272
AOI211_X2 3
AOI21_X1 882
AOI21_X2 3
AOI221_X1 1
AOI221_X2 2
AOI221_X4 33
AOI22_X1 22
BUF_X1 4070
BUF_X16 2
BUF_X2 115
BUF_X4 273
BUF_X8 5
CLKBUF_X2 58
CLKBUF_X3 3
DFF_X1 1514
INV_X1 807
INV_X2 18
INV_X32 5
INV_X4 6
LOGIC0_X1 1
MUX2_X1 1143
MUX2_X2 4
NAND2_X1 1288
NAND2_X2 3
NAND2_X4 1
NAND3_X1 451
NAND3_X2 1
NAND4_X1 84
NAND4_X2 1
NOR2_X1 1262
NOR2_X2 11
NOR2_X4 9
NOR3_X1 335
NOR3_X2 1
NOR3_X4 1
NOR4_X1 58
NOR4_X2 2
NOR4_X4 2
OAI211_X1 356
OAI211_X2 3
OAI21_X1 615
OAI21_X2 1
OAI221_X1 44
OAI22_X1 30
OAI22_X2 1
OR2_X1 228
OR2_X2 5
OR2_X4 2
OR3_X1 236
OR4_X1 111
OR4_X2 1
XNOR2_X1 668
XOR2_X1 873
XOR2_X2 12

Chip area for module '_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy': 25630.164000

S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy_mapped.vPhPtS_PjS_S1_S_S1_S_S1
21. Executing Verilog backend.
Dumping module `_Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy'.

yosys> exit

Warnings: 8 unique messages, 72 total
End of script. Logfile hash: 9dd2f6b66b, CPU: user 35.81s system 0.18s, MEM: 104.99 MB peak
Yosys 0.9+1706 (git sha1 b7419544, gcc 7.4.0-1ubuntu1~18.04.1 -fPIC -Os)
Time spent: 28% 30x opt_clean (9 sec), 17% 25x opt_merge (6 sec), ...
OpenROAD 1.1.0 484b8f0
License GPLv3: GNU GPL version 3 http://gnu.org/licenses/gpl.html

This is free software, and you are free to change and redistribute it
under certain conditions; type show_copying' for details. This program comes with ABSOLUTELY NO WARRANTY; for details type show_warranty'.
Notice 0: Reading LEF file: OpenROAD_objects/merged.lef
Notice 0: Created 22 technology layers
Notice 0: Created 27 technology vias
Notice 0: Created 134 library cells
Notice 0: Finished LEF file: OpenROAD_objects/merged.lef
Startpoint: 34756 (rising edge-triggered flip-flop clocked by clock)
Endpoint: 36070 (rising edge-triggered flip-flop clocked by clock)
Path Group: clock
Path Type: max

Delay Time Description
0.00 0.00 clock clock (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ 34756/CK (DFF_X1)
0.08 0.08 ^ 34756/Q (DFF_X1)
0.17 0.26 ^ 30643/Z (BUF_X1)
0.02 0.28 v 17612/ZN (NOR2_X4)
0.05 0.33 v 17614/ZN (AND2_X4)
0.03 0.36 ^ 17703/ZN (NOR2_X2)
0.02 0.38 v 17719/ZN (INV_X1)
0.05 0.43 ^ 17720/ZN (AOI221_X2)
0.04 0.47 ^ 17721/ZN (AND2_X2)
0.03 0.50 ^ 17727/ZN (AND2_X4)
0.03 0.53 ^ 17749/ZN (AND2_X4)
0.03 0.56 ^ 17750/Z (BUF_X4)
0.04 0.59 ^ 21064/ZN (AND3_X4)
0.04 0.64 ^ 21069/ZN (AND3_X2)
0.04 0.67 ^ 21345/ZN (AND2_X4)
0.03 0.70 ^ 21451/Z (BUF_X8)
0.06 0.76 v 21452/Z (MUX2_X1)
0.03 0.79 v 21453/ZN (AND2_X1)
0.06 0.85 ^ 21456/ZN (AOI211_X2)
0.01 0.86 v 21467/ZN (NOR3_X1)
0.04 0.90 v 21487/ZN (OR2_X1)
0.06 0.96 v 21488/Z (MUX2_X1)
0.03 0.98 v 32559/Z (BUF_X1)
0.00 0.98 v 36070/D (DFF_X1)
0.98 data arrival time

1.00 1.00 clock clock (rise edge)
0.00 1.00 clock network delay (ideal)
0.00 1.00 clock reconvergence pessimism
1.00 ^ 36070/CK (DFF_X1)
-0.04 0.96 library setup time
0.96 data required time
0.96 data required time
-0.98 data arrival time
-0.02 slack (VIOLATED)
Design area 102521 u^2 100% utilization.
Info: Added 428 rows of 3158 sites.
WARNING: force pin spread option has no effect when using random pin placement

Running IO placement

Num of slots 7698
Num of I/O 1173
Num of I/O w/sink 1130
Num of I/O w/o sink 43
Slots Per Section 200
Slots Increase Factor 0.01
Usage Per Section 0.8
Usage Increase Factor 0.01
Force Pin Spread 1
WARNING: running random pin placement
RandomMode Even

IO placement done.
OpenROAD 1.1.0 484b8f0
License GPLv3: GNU GPL version 3 http://gnu.org/licenses/gpl.html

This is free software, and you are free to change and redistribute it
under certain conditions; type show_copying' for details. This program comes with ABSOLUTELY NO WARRANTY; for details type show_warranty'.
Notice 0: Reading LEF file: OpenROAD_objects/merged_padded.lef
Notice 0: Created 22 technology layers
Notice 0: Created 27 technology vias
Notice 0: Created 134 library cells
Notice 0: Finished LEF file: OpenROAD_objects/merged_padded.lef
Notice 0:
Reading DEF file: OpenROAD_results/2_2_floorplan_io.def
Notice 0: Design: _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
Notice 0: Created 1173 pins.
Notice 0: Created 18580 components and 95604 component-terminals.
Notice 0: Created 21186 nets and 58444 connections.
Notice 0: Finished DEF file: OpenROAD_results/2_2_floorplan_io.def
invalid command name "STEP 3: Timing Driven Mixed Sized Placement"
No macros found: Skipping global_placement
fixIoPins.py : Fixing Pins in Def file
Replacements made - West:337 South:249 East:338 North:249
fixIoPins.py : Finished
OpenROAD 1.1.0 484b8f0
License GPLv3: GNU GPL version 3 http://gnu.org/licenses/gpl.html

This is free software, and you are free to change and redistribute it
under certain conditions; type show_copying' for details. This program comes with ABSOLUTELY NO WARRANTY; for details type show_warranty'.
Notice 0: Reading LEF file: OpenROAD_objects/merged_padded.lef
Notice 0: Created 22 technology layers
Notice 0: Created 27 technology vias
Notice 0: Created 134 library cells
Notice 0: Finished LEF file: OpenROAD_objects/merged_padded.lef
Notice 0:
Reading DEF file: OpenROAD_results/2_3_floorplan_tdms.def
Notice 0: Design: _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
Notice 0: Created 1173 pins.
Notice 0: Created 18580 components and 95604 component-terminals.
Notice 0: Created 21186 nets and 58444 connections.
Notice 0: Finished DEF file: OpenROAD_results/2_3_floorplan_tdms.def
No macros found: Skipping macro_placement
##Power Delivery Network Generator: Generating PDN

config: /opt/panda/share/panda//nangate45/pdn.cfg
Design Name is _Z4sailPhPtS_PjS_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S1_S_S_S_yy
Reading BEOL LEF and gathering information ...
****** INFO ******
Type: stdcell, grid
Stdcell Rails
Layer: metal1 - Width: 0.170 Pitch: 2.400 Offset: 0.000
Straps
Layer: metal4 - Width: 0.480 Pitch: 56.000 Offset: 2.000
Layer: metal7 - Width: 1.400 Pitch: 40.000 Offset: 2.000
Connect: {metal1 metal4} {metal4 metal7}
Type: macro, macro_1
Macro orientation: R0 R180 MX MY
Straps
Layer: metal5 - Width: 0.930 Pitch: 40.000 Offset: 2.000
Layer: metal6 - Width: 0.930 Pitch: 40.000 Offset: 2.000
Connect: {metal4_PIN_ver metal5} {metal5 metal6} {metal6 metal7}
Type: macro, macro_2
Macro orientation: R90 R270 MXR90 MYR90
Straps
Layer: metal6 - Width: 0.930 Pitch: 40.000 Offset: 2.000
Connect: {metal4_PIN_hor metal6} {metal6 metal7}
**** END INFO ****
Inserting stdcell grid - grid
Writing to database
Running tapcell...
Step 1: Cut rows...
---- Macro blocks found: 0
---- #Original rows: 428
---- #Cut rows: 0
Step 2: Insert endcaps...
---- #Endcaps inserted: 856
Step 3: Insert tapcells...
---- #Tapcells inserted: 860
Running tapcell... Done!
[INFO] TargetDensity = 0.700000
mkdir: cannot create directory ‘/dev/null’: Not a directory
mkdir: cannot create directory ‘/dev/null’: Not a directory
mkdir: cannot create directory ‘/dev/null’: Not a directory
mkdir: cannot create directory ‘/dev/null’: Not a directory
mkdir: cannot create directory ‘/dev/null’: Not a directory
mkdir: cannot create directory ‘/dev/null’: Not a directory
[PROC] Begin Filling Replace Structure ...
[INFO] DEF DBU = 2000
[INFO] RowHeight = 2800.000000
[INFO] ScaleDownUnit = 311.111115
[INFO] CoreAreaLxLy = (20140.000000, 22400.000000)
[INFO] CoreAreaUxUy = (1220180.000000, 1220800.000000)
[INFO] OffsetCoordi = (2260.000000, 0.000000)
[INFO] ScaleDownRowHeight = 9.000000
[INFO] Modules = 18580
[INFO] Terminals = 2889
[PROC] Begin Generate Nets ...
[INFO] NumNets = 21186
[INFO] NumPins = 59617
[PROC] End Generate Nets
[INFO] Inserted Dummy Terms = 0
[PROC] Begin Generate Rows ...
[INFO] RowSize = (1.221429, 9.000000)
[INFO] NumRows = 428
[PROC] End Generate Rows
[INFO] AspectRatio = 0.998633
[INFO] RowMinXY = (72.000000, 79.264282)
[INFO] RowMaxXY = (3929.271240, 3931.264160)
[INFO] NumPlaceStdCells = 18580
[INFO] NumPlaceMacros = 0
[INFO] RowSize = (1.221429, 9.000000)
[INFO] NumRows = 428
[INFO] GlobalAreaLxLy = (7.489285, 7.489285)
[INFO] GlobalAreaUxUy = (3993.717773, 3996.610596)
[INFO] PlaceAreaLxLy = (72.000000, 79.264160)
[INFO] PlaceAreaUxUy = (3929.271240, 3931.264160)
[PROC] End Filling Replace Structure
PROC: Conjugate Gradient (CG) method to obtain the IP
INFO: The Initial HPWL is 524644.543317
INFO: The Matrix Size is 18580
INFO: IP 0, CG Error 0.000027, HPWL 545957.517281, CPUtime 0.17
INFO: IP 1, CG Error 0.000006, HPWL 526126.977911, CPUtime 0.21
INFO: IP 2, CG Error 0.000001, HPWL 523085.066241, CPUtime 0.22
INFO: IP 3, CG Error 0.000001, HPWL 522274.195831, CPUtime 0.21
INFO: IP 4, CG Error 0.000001, HPWL 521964.732325, CPUtime 0.19
INFO: IP 5, CG Error 0.000000, HPWL 521564.830225, CPUtime 0.21
===HPWL(MICRON)====================================
Mode : Initial Placement
HPWL : 735601.8216
x= 369036.8821 y= 366564.9395
[INFO] TotalPlaceArea = 14858209.000000
[INFO] TotalFixedArea = 18862.050781
[INFO] TotalWhiteSpaceArea = 14839347.000000
[INFO] TotalPlaceMacrosArea = 0.000000
[INFO] TotalPlaceStdCellsArea = 2692896.250000
[INFO] Util(%) = 18.123962
[INFO] 80pCellArea = 139.526581
[INFO] FillerInit: TotalFillerArea = 7694647.000000
[INFO] FillerInit: NumFillerCells = 55146
[INFO] FillerInit: FillerCellArea = 139.533539
[INFO] FillerInit: FillerCellSize = (15.503726, 9.000000)
[INFO] FillerInit: NumCells = 73726
[INFO] FillerInit: NumModules = 18580
[INFO] FillerInit: NumFillers = 55146
INFO: D_MSH = 1024
INFO: MSH(X, Y) = (32, 32)
INFO: dim_bin_cGP2D.(x,y) = (256, 256)
cell Init 2D:
tier->bin_stp: (15.0675 15.0469)
tier->half_bin_stp: (7.5337 7.5234)
PROC: Start NESTEROV's Optimization
PROC: Global Lagrangian Multiplier is Applied
[INFO] Timing: WNS = 1.29948e-11
[INFO] Timing: TNS = 0
[INFO] Nesterov: 0 OverFlow: 0.9854 ScaledHpwl: 3353720.0000
[INFO] Timing: WNS = -9.08862e-12
[INFO] Timing: TNS = -1.37044e-11
[INFO] Nesterov: 10 OverFlow: 0.7612 ScaledHpwl: 4656717.5000
[INFO] Nesterov: 20 OverFlow: 0.7271 ScaledHpwl: 4600205.0000
[INFO] Nesterov: 30 OverFlow: 0.7259 ScaledHpwl: 4532463.0000
[INFO] Nesterov: 40 OverFlow: 0.7285 ScaledHpwl: 4490022.5000
[INFO] Nesterov: 50 OverFlow: 0.7235 ScaledHpwl: 4512176.5000
[INFO] Nesterov: 60 OverFlow: 0.7214 ScaledHpwl: 4498370.5000
[INFO] Nesterov: 70 OverFlow: 0.7225 ScaledHpwl: 4486582.0000
[INFO] Nesterov: 80 OverFlow: 0.7223 ScaledHpwl: 4493103.0000
[INFO] Nesterov: 90 OverFlow: 0.7214 ScaledHpwl: 4493090.0000
[INFO] Nesterov: 100 OverFlow: 0.7219 ScaledHpwl: 4488126.0000
[INFO] Nesterov: 110 OverFlow: 0.7223 ScaledHpwl: 4489798.5000
[INFO] Nesterov: 120 OverFlow: 0.7219 ScaledHpwl: 4492216.0000
[INFO] Nesterov: 130 OverFlow: 0.7219 ScaledHpwl: 4491156.5000
[INFO] Nesterov: 140 OverFlow: 0.7219 ScaledHpwl: 4491949.0000
[INFO] Nesterov: 150 OverFlow: 0.7213 ScaledHpwl: 4494138.0000
[INFO] Nesterov: 160 OverFlow: 0.7207 ScaledHpwl: 4495404.0000
[INFO] Nesterov: 170 OverFlow: 0.7195 ScaledHpwl: 4498037.5000
[INFO] Nesterov: 180 OverFlow: 0.7177 ScaledHpwl: 4502708.0000
[INFO] Nesterov: 190 OverFlow: 0.7145 ScaledHpwl: 4507794.5000
[INFO] Nesterov: 200 OverFlow: 0.7106 ScaledHpwl: 4516302.0000
[INFO] Nesterov: 210 OverFlow: 0.7026 ScaledHpwl: 4528353.0000
[INFO] Nesterov: 220 OverFlow: 0.6926 ScaledHpwl: 4537470.5000
[INFO] Nesterov: 230 OverFlow: 0.6770 ScaledHpwl: 4543792.0000
[INFO] Nesterov: 240 OverFlow: 0.6535 ScaledHpwl: 4535685.5000
[INFO] Timing: WNS = -5.55014e-11
[INFO] Timing: TNS = -5.22214e-10
[INFO] Nesterov: 250 OverFlow: 0.6285 ScaledHpwl: 4530373.0000
[INFO] Nesterov: 260 OverFlow: 0.5989 ScaledHpwl: 4576544.0000
[INFO] Nesterov: 270 OverFlow: 0.5632 ScaledHpwl: 4603646.0000
[INFO] Nesterov: 280 OverFlow: 0.5264 ScaledHpwl: 4607634.0000
[INFO] Nesterov: 290 OverFlow: 0.4824 ScaledHpwl: 4654078.0000
[INFO] Timing: WNS = -1.06277e-10
[INFO] Timing: TNS = -2.22512e-09
[INFO] Nesterov: 300 OverFlow: 0.4519 ScaledHpwl: 4672081.0000
[INFO] Nesterov: 310 OverFlow: 0.4206 ScaledHpwl: 4691820.0000
[INFO] Nesterov: 320 OverFlow: 0.3851 ScaledHpwl: 4693493.0000
[INFO] Nesterov: 330 OverFlow: 0.3558 ScaledHpwl: 4698090.0000
[INFO] Nesterov: 340 OverFlow: 0.3219 ScaledHpwl: 4705394.0000
[INFO] Nesterov: 350 OverFlow: 0.2854 ScaledHpwl: 4708784.0000
[INFO] Timing: WNS = -1.50303e-10
[INFO] Timing: TNS = -2.67458e-09
[INFO] Nesterov: 360 OverFlow: 0.2545 ScaledHpwl: 4708413.0000
[INFO] Nesterov: 370 OverFlow: 0.2222 ScaledHpwl: 4707805.5000
[INFO] Timing: WNS = -1.4887e-10
[INFO] Timing: TNS = -2.59766e-09
[INFO] Nesterov: 380 OverFlow: 0.1903 ScaledHpwl: 4707631.5000
[INFO] Nesterov: 390 OverFlow: 0.1622 ScaledHpwl: 4708060.5000
[INFO] Nesterov: 400 OverFlow: 0.1380 ScaledHpwl: 4708762.5000
[INFO] Nesterov: 410 OverFlow: 0.1158 ScaledHpwl: 4712566.5000
[INFO] Nesterov: 420 OverFlow: 0.0998 ScaledHpwl: 4717579.5000
[INFO] Timing: WNS = -1.53279e-10
[INFO] Timing: TNS = -2.60917e-09
HP wire length: 731895
Worst slack: -1.53e-01
Total negative slack: -2.61e+00
Warning: cell 'OAI211_X1}' not found.
Error: get_property is not an object.
Inserted 1091 input buffers.
Inserted 81 output buffers.
Resized 5488 instances.
Inserted 0 hold buffers.
-------------------- Design Stats ------------------------------
core area : (20140, 22400) (1220180, 1220800)
total cells : 21468
multi cells : 0
fixed cells : 1716
nets : 22360
design area : 1438127936000.000
total fixed area : 1825824000.000
total movable area : 284683840000.000
design utilization : 19.821
rows : 428
row height : 2800
Check Legality
row check ==> PASS
site check ==> PASS
power check ==> PASS
edge_check ==> PASS
placed_check ==>> PASS
overlap_check ==> PASS
-------------------- Placement Analysis ------------------------
total displacement : 62095532
average displacement : 2892
max displacement : 66070
original HPWL : 738875.682
legalized HPWL : 752026.493
delta HPWL : 2%
TritonCTS 2.0 *
Current time: Thu Mar 19 22:26:59 2020

Import characterization *
Reading LUT file "/opt/panda/share/panda//nangate45/tritonCTS/lut.txt"
Min. len Max. len Min. cap Max. cap Min. slew Max. slew
2 8 1 52 1 24
[WARNING] 180 wires are pure wire and no slew degration.
TritonCTS forced slew degradation on these wires.
Num wire segments: 4994
Num keys in characterization LUT: 1677
Actual min input cap: 8
Reading solution list file "/opt/panda/share/panda//nangate45/tritonCTS/sol_list.txt"

Find clock roots *
User did not specify clock roots.
Using OpenSTA to find clock roots.
Looking for clock sources...
Clock names: clock

Populate TritonCTS *
Initializing clock nets
Number of user-input clocks: 1 ( "clock" )
Looking for clock nets in the design
Net "clock" found
clock

Check characterization *
The chacterization used 1 buffer(s) types. All of them are in the loaded DB.
Build clock trees *
Generating H-Tree topology for net clock...
Tot. number of sinks: 1514
Wire segment unit: 20000 dbu (10 um)
Original sink region: [(231990, 315170), (972610, 919970)]
Normalized sink region: [(12, 16), (49, 46)]
Width: 37
Height: 30
Level 1
Direction: Horizontal

sinks per sub-region: 757

Sub-region size: 19 X 30
Segment length (rounded): 10
Key: 3192 outSlew: 1 load: 1 length: 8 isBuffered: 1
Key: 0 outSlew: 2 load: 1 length: 2 isBuffered: 0
Level 2
Direction: Vertical

sinks per sub-region: 379

Sub-region size: 19 X 15
Segment length (rounded): 8
Key: 3206 outSlew: 1 load: 1 length: 8 isBuffered: 1
Level 3
Direction: Horizontal

sinks per sub-region: 190

Sub-region size: 9 X 15
Segment length (rounded): 4
Key: 1170 outSlew: 12 load: 1 length: 4 isBuffered: 1
Level 4
Direction: Vertical

sinks per sub-region: 95

Sub-region size: 9 X 8
Segment length (rounded): 4
Key: 1242 outSlew: 12 load: 1 length: 4 isBuffered: 1
Level 5
Direction: Horizontal

sinks per sub-region: 48

Sub-region size: 5 X 8
Segment length (rounded): 2
Key: 548 outSlew: 2 load: 1 length: 2 isBuffered: 1
[WARNING] Creating fake entries in the LUT.
Level 6
Direction: Vertical

sinks per sub-region: 24

Sub-region size: 5 X 4
Segment length (rounded): 1
Key: 5029 outSlew: 12 load: 1 length: 1 isBuffered: 1
Level 7
Direction: Horizontal

sinks per sub-region: 12

Sub-region size: 2 X 4
Segment length (rounded): 1
Key: 5039 outSlew: 12 load: 1 length: 1 isBuffered: 1
Stop criterion found. Max number of sinks is (15)
Building clock sub nets...
Number of sinks covered: 1514
Clock topology of net "clock" done.

Post CTS opt *
Avg. source sink dist: 46402 dbu.
Num outlier sinks: 3

Write data to DB *
Writing clock net "clock" to DB
Created 258 clock buffers.
Created 258 clock nets.

Current time: Thu Mar 19 22:26:59 2020
... End of TritonCTS execution.
-------------------- Design Stats ------------------------------
core area : (20140, 22400) (1220180, 1220800)
total cells : 21726
multi cells : 0
fixed cells : 1716
nets : 22618
design area : 1438127936000.000
total fixed area : 1825824000.000
total movable area : 287720496000.000
design utilization : 20.032
rows : 428
row height : 2800
Check Legality
row check ==> PASS
site check ==> PASS
power check ==> PASS
edge_check ==> PASS
placed_check ==>> PASS
overlap_check ==> PASS
-------------------- Placement Analysis ------------------------
total displacement : 1657681
average displacement : 76
max displacement : 16853
original HPWL : 763228.133
legalized HPWL : 763580.620
delta HPWL : 0%
Adjust layer 2 in 70.0%
Adjust layer 3 in 70.0%
*** buffer overflow detected ***: openroad terminated`

Build issue

What is the preferred build branch for beta testers?

Following README, I get the following error on executing make from main:

0:fatal error: tcl.h: No such file or directory
#include <tcl.h>

Looks like Ubuntu 18.04 has the tcl.h here: /usr/include/tcl/tcl.h

initialize floorplan overflow

Hello,

I was trying initialize floorplan and specifying -core_area and -die_area. Leading to a floorplan with 0 rows and invalid diearea DIEAREA ( -2147483648 -2147483648 ) ( 0 0 ) ;. I narrowed it down to possible integer overflow while carrying out operations in metersToMfgGrid as follows:

return round(round(dist * dbu * 1e+6 / grid) * grid);

Thanks

Instability in Optimization

Has there ever been a discussion regarding under what conditions RePlAce optimization diverges?
(by diverging I mean the HPWL and overflow starts increasing eventually tripping the early exit above 2e9)

I'm running (at 1.0.0) the superblue benchmarks and I'm finding that more than a few of them are very sensitive to -maxinfl and -inflcoef options and a couple (superblue14, superblue6) are diverging even at the default settings (with routability mode enabled).

In addition, even at the default settings (without any routability optimization enabled) the optimization diverges for superblue2 and superblue3. I've tried changing to 0.9 target density as quoted from the paper but still see divergence.

What are the settings I need to reproduce RePlAce results on these benchmarks? Are there some parameters for which the default is not the correct option for the DAC2012 benchmark?

Running openroad via the PATH environment variable

If I run openroad within the directory where the executable was built, then the tool starts up successfully. However if I move up one directory, then the tool exits as shown in the transcript below

login8.euhpc > openroad
% exit
login8.euhpc > cd ..
login8.euhpc > openroad
Error: could not find FluteLUT files POWV9.dat and POST9.dat.

Seems like the mechanism that the tool uses to find these files should be improved.

pdngen: Non-standard order of layers in VIARULEs

Hello,

So the LEF/DEF reference defines the VIAS section in a DEF file as follows:

[VIAS numVias ; 
[– viaName  
   [   + VIARULE viaRuleName  
          + CUTSIZE xSize ySize  
          + LAYERS botmetalLayer cutLayer topMetalLayer  
          + CUTSPACING xCutSpacing yCutSpacing  
          + ENCLOSURE xBotEnc yBotEnc xTopEnc yTopEnc  
          [+ ROWCOL numCutRows NumCutCols]  
          [+ ORIGIN xOffset yOffset]  
          [+ OFFSET xBotOffset yBotOffset xTopOffset yTopOffset]  
          [+ PATTERN cutPattern] ] 
   | [ + RECT layerName pt pt | + POLYGON layerName pt pt pt] ...] 
;] ... 
END VIAS]

In the golden file you're using, the order of layers in the VIARULEs is bot-top-cut.

I have checked the source code and it seems that pdngen tries to output them in the right order (?), but I haven't dug deeper to see if this traces back to a problem with parsing.

Thanks.

Building openroad branch failed with a fatal error: tcl.h: No such file or directory

openroad commit : 7fa1073 (branch openroad)

Steps to reproduce :

git clone --branch openroad --recursive https://github.com/The-OpenROAD-Project/OpenROAD.git OpenROAD-debug
cd OpenROAD-debug
mkdir build
cd build
cmake -DCMAKE_INSTALL_PREFIX=$HOME/tmp/openroad_install ..
make

cmake correctly locates the tcl lib and header:

 cmake -DCMAKE_INSTALL_PREFIX=$HOME/tmp/openroad_install .. | grep -i tcl
-- TCL library: /usr/lib/x86_64-linux-gnu/libtcl.so
-- TCL header: /usr/include/tcl/tcl.h
-- TCL library: /usr/lib/x86_64-linux-gnu/libtcl.so
-- TCL header: /usr/include/tcl/tcl.h
-- TCL library: /usr/lib/x86_64-linux-gnu/libtcl.so
-- TCL header: /usr/include/tcl/tcl.h
-- TCL library: /usr/lib/x86_64-linux-gnu/libtcl.so
-- TCL header: /usr/include/tcl/tcl.h
-- TCL library: /usr/lib/x86_64-linux-gnu/libtcl.so
-- TCL header: /usr/include/tcl/tcl.h

but build fails with error:

[100%] Building CXX object src/OpenSTA/CMakeFiles/sta_swig.dir/CMakeFiles/sta_swig.dir/StaAppTCL_wrap.cxx.o
cd /home/ronan/perso/github/OpenROAD-debug/build/src/OpenSTA && /usr/bin/c++  -DOPENROAD_BUILD -I/home/ronan/perso/github/OpenROAD-debug/src/OpenSTA/include/sta -I/home/ronan/perso/github/OpenROAD-debug/src/OpenSTA -I/home/ronan/perso/github/OpenROAD-debug/src/OpenSTA/include  -O3 -DNDEBUG   -std=c++11 -o CMakeFiles/sta_swig.dir/CMakeFiles/sta_swig.dir/StaAppTCL_wrap.cxx.o -c /home/ronan/perso/github/OpenROAD-debug/build/src/OpenSTA/CMakeFiles/sta_swig.dir/StaAppTCL_wrap.cxx
/home/ronan/perso/github/OpenROAD-debug/build/src/OpenSTA/CMakeFiles/sta_swig.dir/StaAppTCL_wrap.cxx:166:10: fatal error: tcl.h: No such file or directory
 #include <tcl.h>

Running cmake with TCL_HEADER option gives the same error

( cmake -DCMAKE_INSTALL_PREFIX=$HOME/tmp/openroad_install -DTCL_HEADER=/usr/include/tcl/tcl.h .. )

Apparently, the top level information about TCL file location is not propagated correctly down to OpenSTA

tapcell overlap with endcap

Hello,

Using tapcell tool to insert tapcells and decaps cells, depending on the input distance and the design size, can lead to overlapping tapcells with the right decap column. Please check with @tspyrou for a private repo for a test case.

Thanks

Build error with tclreadline patch

Thanks for including the readline.
When I pulled and compiled the new commit (1635259) I get a compile error: 'std::array' is not a member of 'std'. To correct this Main.cc needed to have #include included along with the tclreadline.h.
This was on a Ubuntu 20.04 install.

[TritonCTS] Exiting on trivial designs with 1 sink

TritonCTS currently skips nets which have 1 sink, which makes sense because a tree cannot be constructed with 1 sink:

if (clockNet.getNumSinks() < 2) {
std::cout << " [WARNING] Net \"" << clockNet.getName() << "\""
<< " has " << clockNet.getNumSinks() << " sinks. Skipping...\n";
return;

However, for trivial designs which have only 1 sink, this results in no clock nets being found and TritonRoute will exit on error:

if (getNumClocks() <= 0) {
std::cout << "\n";
std::cout << " [ERROR] No clock nets have been found.\n";
std::exit(1);
}

TritonCTS should be able to handle this case. I think the main thing is that TritonCTS should never call std::exit, it should return control to the main openroad app and allow the app decide what to do.

Even if TritonCTS returns and does nothing (other than issue WARNs and/or ERRORs), this is a tautological case that should not cause OpenROAD to exit.

Here is an example design (credit to @ax3ghazy):

module andd
(
  input  wire clk,
  output reg c,
  input  wire a,
  input  wire b,
  input wire reset
);

    wire x;
    assign x = a & b;

always @(posedge clk)
    if(reset)
        c <= 1'b0;
    else
        c <= x;
endmodule

And the resulting log:

 ************************
 *  Populate TritonCTS  *
 ************************
 Initializing clock nets
 Number of user-input clocks: 1 ( "clk" )
 Looking for clock nets in the design
 Net "clk" found
clk
    [WARNING] Net "clk" has 1 sinks. Skipping...
    [ERROR] No valid clock nets in the design. Exiting...

Segfault in test-1-large-pin-count test-case

To reproduce:

Get this pull request for alpha-release: The-OpenROAD-Project/alpha-release#28

Then run:

# cd alpha-release/flow/
# make DESIGN_CONFIG=designs/test-1-large-pin-count.mk
[deleted]
INFO:  Now linking: LargePinCount
INFO:  Successfully linked: LargePinCount
NO PATH !
INFO: Total 0 worst path!
/bin/bash: line 17:    69 Segmentation fault      (core dumped) RePlAce -bmflag etc -lef ./objects/nangate45/LargePinCount/merged_padded.lef -def ./results/nangate45/LargePinCount/2_floorplan.def -verilog ./results/nangate45/LargePinCount/2_floorplan.v -lib ./platforms/nangate45/NangateOpenCellLibrary_typical.lib -sdc ./results/nangate45/LargePinCount/2_floorplan.sdc -output ./results/nangate45/LargePinCount/replace -t 1 -timing -resPerMicron 1.59 -capPerMicron 0.235146e-12 -skipIP -plot -experi output -den 0.509 -initCoef 0.00002 -onlyGP 2>&1
        70 Done                    | tee ./logs/nangate45/LargePinCount/3_1_RePlAce.log

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