vvbandeira Goto Github PK

abc

ABC: System for Sequential Logic Synthesis and Formal Verification

actions

actions-test

caravel_user_project

https://caravel-user-project.readthedocs.io

chips-2.0

FPGA Design Suite based on C to Verilog design flow.

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

datc-rdf-metrics4ml

gcloud_test

google-cloud-python-examples

Python examples on Google Cloud Platform (GCP). How to manage Compute Engine VM instances, Cloud Storage buckets, etc.

gsoc-tutorial-example

log4jscanner

A log4j vulnerability filesystem scanner and Go package for analyzing JAR files.

lsoracle

IDEA project source files

openlane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

openlane-mpw-ci

openroad

OpenROAD's unified application implementing an RTL-to-GDS Flow

openroad-flow-scripts

runner

The Runner for GitHub Actions :rocket:

security

spectacle

Spectacle allows you to organize your windows without using a mouse.

uccross.github.io

CROSS Repositories Web Site

ucsc-ospo.github.io

Website of the Open Source Program Office, UC Santa Cruz

vim-dispatch

dispatch.vim: Asynchronous build and test dispatcher

xls

XLS: Accelerated HW Synthesis

xmanager

A platform for managing machine learning experiments

yosys

Logic synthesis and ABC based optimization