sheldonucr / ucr-eecs168-lab Goto Github PK

When doing the simulation for the testbench, for both A and B input pulse voltages, do we have to change the periods to get different outputs to test the NAND gate? Also instead of ground, what should I put for VSS? A bit stuck trying to find the right timings to get all NAND gate results.

I am trying to login to bender to finish the lab 3 report but my access is denied. I have tried around 10 times and I am sure my password is correct. Is there something wrong with bender at the moment?

I've passed the DRC check for my system. My issue occurs when I run the LVS check. On the Console Window it shows that the LVS results are clean. However, on a different window it shows that there are unmatched nets, etc. Which one should I listen to and why are they contradicting each other?

I cannot open any of the schematic/designs I have created that are in mylibrary even though the file is in my eecs168 folder and I opened cdesigner in the eecs168 folder. I cannot even access mylibrary on cdesigner

I am passing DRC but having LVS errors. I have rebuild the lab thinking I did something wrong but I am still getting same issues and can't figure out why I am having these errors.

I'm not sure how to fix this as the AVSS is shorted with gnd! in the lab directions

My NAND gate simulation keeps failing, and I can't make heads or tails of the error. I've recreated the schematic, the symbol, and the testbench and it doesn't seem to change anything. The "Check and Save" doesn't flag any errors, and the only description of the errors I can find is in the screenshot below.

I was wondering if there is a way to copy the elements, such as the PMOS and the NMOS, onto a new gate layout page for part 8 of the lab?

Hi,
I have this warning while Syntax error checking:

After running the transient analysis, I pass the tests but the waveform does not appear. It says I am missing a library or something? I have no idea what the issue is

Hey, I'm having some issues with my lab3 design. Are you guys available today for some questions? Thanks.

Response when I try to launch cdesigner.

For some reason I'm getting an 4 errors regarding "Min enclosure of contact at end of line." I'm confused because the layout I met for those errors seem to meet the requirements of .005 um as shown in the picture below. I measured/used the ruler for the ones that got this error and they all measured to be .005um on each side. I'm not sure what to do - any help is appreciated, thank you!

So I submitted the first time but it won't let me submit a second time since I forgot to attach a file. I am not sure what to do?

Hi,

I am having some trouble with lab 2.
Can you spare some time to help me if I come to the office 1-5pm?

Thank you

I was having an issue with the command
report_resources -nosplit -hierarchy

It tells me that
command 'report_resources' is disabled (CMD-080)

I apologize if this was asked and I didn't see, but if we didn't finish the lab in-lab, do we make an appointment to demonstrate we finished it to get it checked off, or could we send an email of what we did?

I was going to try and work more on lab 3 when I noticed I couldn't open any of my files in a writable mode. Cdesigner only allows me to access them in Read-Only mode. Anyone know how to fix this?

I can log in to bender, but when I use "cdesigner&" command to test it I get the following error,

[1] 26628
bender /home/eemaj/lugarcia $ Error: DISPLAY environment variable is not defined.

What do we do if we're a CS student and have a CS account, but not an ENGR account?

I am not able to get any output when running the simulation with the capacitance loaf of 0.05p F, but if I were to remove the capacitor all together, I am able to get an output with some noise.

Am I not using the proper element to filter correctly, or is there something wrong with my schematic?

Hey Guys,

I keep getting an error with these commands!
wget https://raw.githubusercontent.com/tkimva/ucr-eecs168/master/lab4/counter.v
wget https://raw.githubusercontent.com/tkimva/ucr-eecs168/master/lab4/counter_tb.v
I get "ERROR 404: Not Found"
Any pointers?

Thanks!

After the 1 bit full adder's DRC and LVS simulation are done. Do we need to do the parasitic extraction for the 1 bit full adder? I am a bit confused on if it is needed to complete the 4 bit full adder. Or we can just start on the 4 bit adder and then do the 4 bit full adder parasitic extraction without doing the parasitic extraction for the 1 bit full adder.

Hey I'm having issues with the lvs and can't seem to locate the problem. Could you help me with this?

I have a interview today at 1. I might be able to come for the the first half hour or hour of lab. Will I be marked off because of this?

I am currently trying to output the proper waveforms but keep getting jumbled stuff for my output. Do we need capacitative loads to filter any noise? If so, how much capacitance. (P.S. I already tried .05 pF loads at each output, and it still looks like crap)

I'm having issues getting my code to pass the test bench. I thought we went through all my code and validated it in lab but I guess there are some errors still. Could you take a look at my code? I've attached the three files
Lab.zip

For the 1-bit adder layout, there is so much going on that my paths overlap and I haven't tested it yet but I am pretty sure it will be a problem. Is there a way to do virtual connections in layouts? Like name the inputs the same name so they get treated as the same?

Hello, any ideas on how to fix this error? I get it when I try to run the Netlist and Run simulation.
-Thanks!

I have an error that I have no idea how to fix. It passes DRC but I get one error when I run LVS:
I put the screen shot of my error and layout

I think I left my wireless mouse and keypad in the lab room today after lab at the table in the back corner of the room. Did you or anyone else happen to see it?

For #4 a) I don't understand why the best case for pmos is 3/4 and 4/3 for nmos. I thought the best case was the least amount of mos you have to go through. So shouldn't that make it 1 for pmos and 2 for nmos?

If I am getting an error saying,

"There are 4 unmatched nets in the schematic."
"There are 4 unmatched nets in the layout."

Does this mean that the schematic and layout do not match?

Hi,

I keep getting an error with LVS that I have a shorted net on my layout with gnd! and AVSS.

Also the same with AVDD and vdd!

I'm a little lost on how to fix this

Trying to open up the testbench for my 1bitadder so i can include it in my report, but i keep getting this error.

The text in lab two that reads More details can be founded at is immediately followed by a broken link.

I was able to upload my homework and clicked submit. I waited over 15 minutes and it didn't go through. I tried submitting from a different laptop and I'm still having trouble submitting.

Can you allow multiple submissions on ilearn? I submitted my finished lab4 on Friday, and since then I've finished the full-chip synthesis extra credit and would like to submit the lab again with this included.

Hi,

Just out of curiosity, do you have an idea on when grades will be posted/finalized?

Hello,
I deleted all of the .cdslck files in my EE168 folder in BENDER. After I cdesigner& and log in. I go to open recent. On top of my schematic it still says reader mode. Any suggestions on what I can do next?

I have no errors when running my test-bench but it does not look like the one in the lab manual. Any hints on what I may be missing?

Hi everyone,

Unfortunately ilearn had an issue with cross listed classes this quarter. Because of this, they created an EE168 and a CS168. They are now in the process of consolidating all the cross listed classes for the entire school. It seems during this process the CS168 ilearn listing was removed so those of you who were added to that ilearn listing likely no longer have access to it.

Hopefully they finish this consolidation soon. We will keep monitoring the situation and make sure to keep you all informed the best we can.

When will the Midterm and other Homework assignment solutions be put up in iLearn?

I want to make sure I have access to those when I am studying for the exam this Thursday.

The last sentence in the first paragraph of section labeled Part 10: Post Layout Simulation has misleading information. The instruction is to open the inverter circuit schematic when it should say to open the inverter testbench circuit schematic. This error is repeated several times until finally corrected in the Fig. 74 label.

We are having trouble running the testbench. We can't get the right AIN and BIN vpulse wave forms. We set the AIN and VIN vpulse's to the same properties as lab 1 except changed the specified pulse width to what was said on the lab. Are these the right settings? This is what we get.

We think it's from setting up the dc analyses from the SAE. We have 2 vpulse's AIN and BIN, but when setting up the dc sweep on the Transient Simulation Setup we don't know what settings to use since we have 2 vpulses and the setup asks you to choose only 1. On this part.

Hi,
When I set my input pulses in SAE, I faced the following error:
Expression 'v(/B)' did not evaluate: No results found

I am having some problems testing with the LVS. I believe it may be one of two problems. The Diff in my lab1 has height = 0.5um and 0.25 um. I know the lab states this should be the width but the pictures show that it is really the height. This is one problem.

Another is that in lab 1 I could not find the right PMOS and NMOS (M0, M1) so I used M9 and M10. I am wondering if either of these are possible problems. If not, could you help me figure out what I am doing wrong?

My project passed the DRC test.

Thank you

I find that LVS in cdesigner does not check the crucial parameters of transistors. So I am writing this post to remind you of this problem.

Take our inverter layout as example. The NMOS in the layout below has parameters: W=0.25um, L=0.1um.

In this figure, the parameters of the NMOS is changed to: W=0.4um, L=0.1um.

The issue is that both layouts will pass LVS. However, we know that only the one with the correct parameters should match. So please keep in mind what stands for width/length for transistors in a layout and try to make it correct in the first place, as we cannot rely on LVS for this problem in our labs.

I after doing the transient simulation I got this result:

I'm not sure if it is the correct output but the relationship between a,b and the output seems to be right.

Also, where can I find the NAND gate layout? It says it's on the lecture notes but I couldn't find it. I may have overlooked it, though.

Thank you!

Does anyone know how to enable the resources report command in IC Compiler?

I only need this last report.