How to deal with overlapping paths? about ucr-eecs168-lab HOT 1 OPEN

No, there are no virtual connections. Layout is a physical design step. You are creating the actual template that the foundry will look at to create a real chip, as such, there is nothing "virtual" about this process. Each material you place will be a real physical thing configured based on the layer it belongs to.

Now, if you think of everything in terms off layers, we can actually find a solution to help us. The thing is, we are not restricted to just poly( lowest layer of interconnect) and metal 1( lowest layer of metal but above poly). In fact, we can make use of a dozen more layers of metal. If you look in the lab instructions, there is a small section that tells you how to make use of metal 2 ( one layer up above metal 1 ). If you really wanted, you could use even more but it wouldn't be necessary. Make smart choices in how you do your layout and these layers should be plenty to avoid conflicts.

from ucr-eecs168-lab.