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sorear avatar sorear commented on July 2, 2024

How about t0 or t1? Then we could change Linux as well, and it'd be slightly cleaner to not have the call selector stepping on one of the argument registers.

We would still need to define what the calling convention is on RV32E. There are tradeoffs that happen differently with just 15 registers…

from riscv-elf-psabi-doc.

aswaterman avatar aswaterman commented on July 2, 2024

From the manual: "The privileged architecture of an RV32E system can include user mode as well as machine mode, and the Mbare, Mbb, and Mbbid memory management schemes described in Volume II."

RV32E is meant for embedded systems that don't host an OS, so the choice of a7 doesn't matter. If you can afford the primary and secondary storage necessary to host Linux, you can afford the additional 16 registers (and probably will get better energy per operation from having them). My preference is to take no action on this matter.

If we did take action, a5 would not be ideal, since mmap takes 6 args and so already uses a5. t0 is probably fine.

from riscv-elf-psabi-doc.

kito-cheng avatar kito-cheng commented on July 2, 2024

Humm, so we will implement that in t0 for newlib and gdb sim.

@sorear RV32E seem only 3 callee save register(and 1 for $sp), do you think need to make it more balance?

from riscv-elf-psabi-doc.

sorear avatar sorear commented on July 2, 2024

@kito-cheng I have absolutely no idea. Build SPEC with various ratios of caller to callee saves and pick whichever one minimizes code size?

from riscv-elf-psabi-doc.

aswaterman avatar aswaterman commented on July 2, 2024

My work on RVC resulted in x8-15 being s0-1 and a0-5. Point being, having RVC target 2 saved and 6 argument registers minimized code size, moreso than 3 saved and 5 argument, for example. So I'd leave it as-is.

Also, we want the register map for RV32E to match RV32I if at all possible to minimize confusion.

from riscv-elf-psabi-doc.

michaeljclark avatar michaeljclark commented on July 2, 2024

Just noting that the PLT header and stubs use t3 for shared library calls. I wonder if the stubs can be reworked to use t0 through t2. This is a separate issue to the syscall ABI.

from riscv-elf-psabi-doc.

aswaterman avatar aswaterman commented on July 2, 2024

I highly doubt dynamic linking will be popular on RV32E systems, but yeah, it looks possible.

from riscv-elf-psabi-doc.

kito-cheng avatar kito-cheng commented on July 2, 2024

It should be target / OS specific things, so I think we are not going to document on psABI.

from riscv-elf-psabi-doc.

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