Comments (7)
Well for starters that doesn't work for RV32 and we don't want gratuitous ABI divergence between the two, which this would be.
from riscv-elf-psabi-doc.
We can define a relocation with the "relaxable" bit as equivalent to a pair of the original relocation and a R_RISCV_RELAX
pointing to the same location. In other words, the "relaxable" bit is just shorthand notation for two relocations and nothing more. BFD ld would actually handle it in that manner.
from riscv-elf-psabi-doc.
I think I have undergone a mindset shift regarding R_RISCV_RELAX. Initially, I'd use a fixed bit as well, provided we had the opportunity to redesign linker relaxation. The fact that ELFCLASS32 has a limit of 256 is not a significant issue. We can simply use composed relocations for niche types.
However, the idea of supporting the RVC/non-RVC difference (#393) makes me reconsider that R_RISCV_RELAX might not be as problematic as I initially thought. To minimize waste, we should consider reducing R_RISCV_RELAX for instructions that are used as a unit. Currently, some relaxable code sequences require each instruction to be paired with a R_RISCV_RELAX, which is inefficient.
from riscv-elf-psabi-doc.
We have to consider Zcmt and the Andes LWGP etc extension as well, possibly extensions that will affect relaxation of common symbol references.
from riscv-elf-psabi-doc.
I inclined to the approach proposed by #393, which using ISA string to record the info, I think that could carry more information to resolve RVC/non-RVC issues.
from riscv-elf-psabi-doc.
If we wanted to go down this path, I think it would make more sense to define a shorthand relocation record and a new sh_type value for shorthand relocations (vaguely similar to the approach taken with DT_RELR) which would provide substantially less than 64 bits of offset and addend in addition to providing a 1-bit relaxation indicator. Any relocation record which does not fit in the offset/addend/type fields, or which requires more than 1 bit to indicate its relaxation properties, would need to use the full relocation record.
from riscv-elf-psabi-doc.
My CREL proposal will make .o size significantly smaller without embedding.
https://discourse.llvm.org/t/rfc-crel-a-compact-relocation-format-for-elf/77600
build format .o size size(.rel*) .o size decrease
x86_64 -O3 RELA 136012504 28235448
x86_64 -O3 CREL 111583312 3806234 18.0%
aarch64 -O3 RELA 124965808 25855800
aarch64 -O3 CREL 102529784 3388307 18.0%
ppc64le -O3 RELA 129017272 26589192
ppc64le -O3 CREL 105860576 3432419 17.9%
riscv64 -O3 RELA 227189744 91396344
riscv64 -O3 CREL 149343352 13549699 34.3%
I started llvm-project patches for CREL. Relocatable file size isn't a major concern for a few folks on https://groups.google.com/g/generic-abi/c/yb0rjw56ORw
from riscv-elf-psabi-doc.
Related Issues (20)
- Specify relocation overflow checks HOT 1
- Specify a platform reserved register HOT 20
- Should calling convention also define ptrdiff_t? HOT 1
- Should we use lw/sw in push pop when we used ILP32, whether it's RV32 or RV64 HOT 3
- Operation semantics of __bf16 datatype HOT 2
- representation of GNU C fixed-size vectors HOT 4
- Deprecate R_RISCV_RVC_LUI? HOT 4
- Define GOT-Relative data relocation HOT 8
- Define gp(x3) as global VLENB HOT 4
- Bitfield integer calling convention garbled
- Calling convention uses RV64GQ without definition or reference HOT 3
- Calling convention description of va_list et al. are unclear HOT 2
- Interpretation of floating-point types
- Linux ABI for Pointer Masking HOT 19
- New ABI for stack layout and frame pointer scheme HOT 4
- Change branch from "master" to "main" HOT 1
- Add CREL support HOT 3
- Add RELR support HOT 6
- Question about medlow's single 2 GiB address range HOT 1
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from riscv-elf-psabi-doc.