Use synonyms in order to treat situation when manufacturer's company name changes after acquisition.

Hi!

Since es6 there isn't really much reason imo to continue using coffescript. Migrating to es6 would potentially increase the developer base.

Would a PR that decaffeinates the code base have any chance at being merged?

Thanks,
David

[0] https://github.com/decaffeinate/decaffeinate

The QEDA created courtyard layer drawings are not compatible with the newest KiCad version. I get this error at DRC: ErrType(46): Footprint has incorrect courtyard (not a closed shape)
The problem is the centroid sign on the courtyard layer, like this one:

  (fp_circle (center 0.000 0.000) (end 0.000 0.500) (layer F.CrtYd) (width 0.050))
  (fp_line (start -0.700 0.000) (end 0.700 0.000) (layer F.CrtYd) (width 0.050))
  (fp_line (start 0.000 -0.700) (end 0.000 0.700) (layer F.CrtYd) (width 0.050))

I think it would be better to not have a centroid at all, as manufacturers don't need this anymore for assembly. But if someone needs it, it should move to another layer like "F.Fab", and be optional.

A svg backend would be really useful. This would add support for generating schematics using netlistsvg.

[0] https://github.com/nturley/netlistsvg
[1] https://raw.githubusercontent.com/nturley/netlistsvg/master/lib/analog.svg

Connector schematic symbol generation need to be improved.

The npm package is fairly outdated (8 years old) at the moment. @shamil-ru, do you have access to the account to update it? If not, could you get in touch with whoever has the necessary access?

When schematic symbol is generated to the attached part, many pins are duplicated. Another problem is that in this case some pins are placed outside of the IC symbol's rectangle.
A workaround could be that I only use a signal name once, but that would not be correct. According to the part's datasheet (page 35), the same signals can be accessed through multiple pins (with software configuration).
Anyways, if something is not correct in the .yaml file, an error message would be nicer than generating a messed-up part...
mkl02z32caf4r.yaml.zip

I would really appreciate if you can give a quick solution, because I have a very tight deadline on this project. Thanks!
Btw, I love the concept of QEDA!

in last kicad sources I've found such definition:

https://github.com/KiCad/kicad-source-mirror/blob/master/eeschema/class_library.h
line 74

/* Must be the first line of part library document (.dcm) files. */
#define DOCFILE_IDENT     "EESchema-DOCLIB  Version 2.0"

with two spaces between DOCLIB and Version

current .dcm cause a error parsing it:

ading space fix this error

I tried to create a BGA housed FET in QEDA, but I get a broken schematic symbol:

It would be nice to have G, D, S signs on the legs instead of numbering, as for the BGA component numbering is ugly and not useful at all. Also please allow substrate (thermal, not connected or connected to Source) pads.

I made a custom housing as the BGA pattern does not allow custom pad numbering scheme.

The epc2047.yaml is this:

name: EPC2047
description: eGaN FET, 200V, 10mΩ
datasheet: http://epc-co.com/epc/Portals/0/epc/documents/datasheets/EPC2047_preliminary.pdf
keywords: eGaN, GaN, FET

pinout:
  G: 1
  D: 3, 4, 5, 9, 10, 11
  S: 2, 6, 7, 8, 12, 14
  sb: 13 # = substrate

properties:
  in: G
  passive: S, D, sb

schematic:
  symbol: FET
  options: n, diode

housing:
#  pattern: BGA # WLCSP
#  leadCount: 14 # 14
#  rowCount: 3
#  columnCount: 5
#  horizontalPitch: 1.0
#  verticalPitch: 0.5
#  leadDiameter: 0.330
  pattern: custom
  bodyLength: 1.570-1.630
  bodyWidth: 4.570-4.630
  height: 0.790
  padDiameter: 0.330
  padWidth: 0.330 # workaround for QEDA bug, can be deleted later
  padHeight: 0.330 # workaround for QEDA bug, can be deleted later
  padPosition: -2, -0.5, -2, 0.5, -1, -0.5, -1, 0, -1, 0.5, 0, -0.5, 0, 0, 0, 0.5, 1, -0.5, 1, 0, 1, 0.5, 2, -0.5, 2, 0, 2, 0.5

Would there be any interest in adding an optional SPICE model within the library or an option to link to an external SPICE model (now that KiCAD is offering built-in simulation...)?

Similarly, any plan to provide links to .STEP models for MCAD?

It would be nice to have an option for telling QEDA which naming convention to use for footprint generation.

• IPC-7351B - for compatibility with old designs
• IPC-7351C - for new designs, also it should be the default setting

I think, it would be nice to be able to define custom footprint names too at housing level. It would be especially useful for exotic footprints, where pattern: custom is used in housing.

Changes are to be supported:

• Land pattern naming conventions
• New pad calculation rules
• Silkscreen updates
• Terminal leads to mechanical layer

Add connection.url parameter in order to point custom source of component descriptions.

No 3d models being generated yet. Is this still in the planning stage?

Can I use custom git repo for 'qeda load' command? I clone original 'qeda/library' repo, and want to use it.

Symlinking to project's './library' catalog is not good idea - any 'qeda load' command can silently replace files in my working repo

Currently, it is relatively inconvenient when you want to keep track of components like capacitors, where a lot of different variations of a component exist. To keep my library somewhat clean, I currently use varitions for this. E.g. I have a SMA-A0102FTDL.yaml with many lines similar to:

name@10R: SMA-A0102FTDL10R
value@10R: 10

name@12R: SMA-A0102FTDL12R
value@12R: 12

name@15R: SMA-A0102FTDL15R
value@15R: 15

It would be nice if I were able to condense this down a bit. Related to this, many components have essentially multiple levels to their part numbers.

In order to simplify the file structure and managing values inside a file, I suggest a multi-level suffix system.

• First of all, rather than only having suffix, I would like to introduce suffix1, suffix2, ... Here, the number after the suffix tells qeda in which order to apply them. If numbered suffixes are used, suffix without any number should return a warning and be ignored.
• Secondly, I reckon it would be great to have a shorthand way of defining multiple value-variations without having to list them individually. A suggestion that would be fairly straight-forward to implement (with values set, value would be ignored) and easy to use:

values:
  10:
    suffix1: 10R
    description_append: ", 10Ω"
  12:
    suffix1: 12R
    description_append: ", 12Ω"
  15: {suffix1: 15R, description_append: ", 15Ω"}

Please let me know your thoughts. (@shamil-ru @cuvoodoo)

We set final diameter of metalized hole, not drill diameter.

GOST styled IC symbols generated by QEDA are not 100% compliant to ESKD.
The main complaint here are main body dimension and lack of IC descriptor.

1. Main body dimensions.
   The main body is the middle empty part of IC symbol body. It should be at least 10 mm wide. QEDA generates it too small (5 mm or less).
2. IC descriptor
   Every IC symbol should have IC descriptor inside it's main body. It's either a specific symbol or letter code.
3. IC name.
   This one is optional.
   IC name should be placed inside main body under IC descriptor. But it is often placed under the main body.

Example:

Generated:

Should be:

There is a new pad shape option in KiCad (in the nightly build version): Rounded Rectangle.
It is the preferred pad shape in the IPC-7351C standard, so it would be useful if QEDA had this option under housing.

• the default corner radius is 25% of the leadWidth
• the default maximum radius is 0.25mm

A pad example with this property looks like this in the .kicad_mod file:
(pad 1 smd roundrect (at 1.5 1.1) (size 2 1.524) (layers F.Cu F.Paste F.Mask)(roundrect_rratio 0.25))

There are some parts with QFN package, where the leads at the corner would normally be too close (or even overlap sometimes), due to the small body size. These packages usually define a corner lead-to-lead spacing parameter, and the corner pads are cut in 45° at a position calculated from the spacing.
Some examples:
https://www.invensense.com/wp-content/uploads/2015/03/ICM-30630_ProductSpec_V1.0.pdf
https://www.invensense.com/wp-content/uploads/2016/06/DS-000189-ICM-20948-v1.1.pdf
https://store.invensense.com/datasheets/invensense/PS-ITG-3400A-00.pdf

It would be nice to have an optional cornerLeadSpacing parameter for covering these cases instead of creating custom packages.

Ругается, если в housing есть suffix, как в ti/lm158:

di@ubuntu:~/Workspace/pa-01/schemes$ qeda --version
QEDA v0.2.0
di@ubuntu:~/Workspace/pa-01/schemes$ qeda generate wa
Read 'capacitor/c0603'
Read 'capacitor/c1210'
Read 'capacitor/c0805'
Read 'resistor/r0805'
Read 'misc/tp-th-1'
Read 'st/stm32f030c'
Read 'ti/lm158'
/usr/local/lib/node_modules/qeda/lib/qeda-library.js:110
        suffixes = obj.housing.suffix.replace(/\s+/g, '').split(',');
                                     ^

TypeError: Cannot read property 'replace' of undefined
    at QedaLibrary.add (/usr/local/lib/node_modules/qeda/lib/qeda-library.js:110:38)
    at generateLibrary (/usr/local/lib/node_modules/qeda/bin/qeda:155:9)
    at Object.<anonymous> (/usr/local/lib/node_modules/qeda/bin/qeda:302:5)
    at Module._compile (module.js:410:26)
    at Object.Module._extensions..js (module.js:417:10)
    at Module.load (module.js:344:32)
    at Function.Module._load (module.js:301:12)
    at Function.Module.runMain (module.js:442:10)
    at startup (node.js:136:18)
    at node.js:966:3

Platform: WinXP SP3 x32
Node v5.12.0
npm v3.8.6

commands

qeda reset
qeda config symbol.style 'GOST'

generatess following .qeda.yaml file:

config:
symbol:
style: '''GOST'''

And if I change 'GOST' to GOST or "GOST" it is generated as

config:
symbol:
style: GOST

Both variants are ignored by "generate" and "test" commands and QEDA creates default style symbols.
The same happens with symbol.style 'default' command, but it does not affect anything.

Manually changing '''GOST''' into 'GOST' in .qeda.yaml file fixes this problem but is not convenient to do.

For most of the housings there are padLength and padWidth parameters. But if I choose pattern: custom, instead of padLength there is padHeight. I think, it is a mistake.
There is also another error in https://github.com/qeda/qeda/blob/master/src/pattern/default/custom.coffee
in line 14:
padDiameter is missing from this condition.

Is it possible to change the place for the downloaded Libraries?
I don't like it when the OS /Library folder get populated with all the new folders for the downloaded libraries.
If not make at least a folder /Library/qeda/ where you put all the downloaded stuff.

Thanks in advance

Add symbol.resemblePattern boolean parameter which make component with dual-side or quad-side pinout have schematic symbol layout resembling its land pattern.

KiCad version: 5.0.0
Everything looks good while viewing the symbol in the library:

But after adding a symbol to the schematics, descriptor is moved beyond it:

Attached test.yaml expected to generate 8-pin IC symbol: left side pins 1-4, right side others. But it generates only 4 pins.
test.yaml.txt

Add housing.bodyColor parameter support.

There is an error in through-hole pad generation. The created .kicad_mod file has this layer definition for through-hole pads: (layers F.Cu F.Mask F.Paste B.Cu B.Mask B.Paste). We definitely do not want paste on holes.
I think this would be the correct layer definition: (layers *.Cu *.Mask). (It would include the inner layers too.)

Add fiducials for the fine pitch QFP and BGA packages according to IPC-7351

lines with empty ALIAS property in .lib files generate errors in kicad for windows (nightly build. I know :)

for example command qeda test capacitor/c0603
generates such library:

EESchema-LIBRARY Version 2.3 Date: 17/10/2016 15:35:34
#encoding utf-8
#
# C0603
#
DEF C0603 C 0 40 N N 1 L N
F0 "C" 0 110 50 H V C BNN
F1 "C0603" 0 -110 50 H V C TNN
F2 "test_c0603:CAPC1608X92M" 0 0 0 H I C CNN
ALIAS 
$FPLIST
  CAPC1608X92M
$ENDFPLIST
DRAW
X 1 1 -100 0 85 R 50 50 1 1 P
X 2 2 100 0 85 L 50 50 1 1 P
P 2 1 1 12 -15 80 -15 -80 N
P 2 1 1 12 15 80 15 -80 N
ENDDRAW
ENDDEF
# End Library

removing empty ALIAS line cancels this error

qeda 0.2.6
kicad:

Application: kicad
Version: (2016-09-17 revision 679eef1)-makepkg, release build
Libraries: wxWidgets 3.0.2
           libcurl/7.46.0 OpenSSL/1.0.2d zlib/1.2.8 libidn/1.32 libssh2/1.6.0 librtmp/2.3
Platform: Windows 7 (build 7600), 64-bit edition, 64 bit, Little endian, wxMSW
- Build Info -
wxWidgets: 3.0.2 (wchar_t,wx containers,compatible with 2.8)
Boost: 1.57.0
Curl: 7.46.0
KiCad - Compiler: GCC 5.2.0 with C++ ABI 1009
        Settings: USE_WX_GRAPHICS_CONTEXT=OFF
                  USE_WX_OVERLAY=OFF
                  KICAD_SCRIPTING=ON
                  KICAD_SCRIPTING_MODULES=ON
                  KICAD_SCRIPTING_WXPYTHON=ON
                  BUILD_GITHUB_PLUGIN=ON
                  KICAD_USE_SCH_IO_MANAGER=ON
                  KICAD_USE_OCE=ON

For matching components using electro-grammar it would be useful to add datasheet parameters like vf, ic, beta, bwp, sr to component definitions.

[0] https://github.com/monostable/electro-grammar

Many new WLCSP packages are staggered pin BGAs, it would be nice if QEDA will support it. They already have IPC-7351C name definition, starting with BGAS.
Some examples:

• page 8 of http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42493-ATBTLC1000-WLCSP-SOC_Datasheet.pdf
• last page of http://www.onsemi.com/pub_link/Collateral/BELASIGNA300-D.PDF

Platform: WinXP SP3 x32
Node v5.12.0
npm v3.8.6
qeda v0.3.8

I was trying to make GOST styled symbol with 5.08 mm long pins spaced by 5.08 mm, 3mm high RefDes and 2.54 high PinNames and PinNumbers and discovered a whole set of problems connected to symbol.gridSize.

First: Everything is tied to grid size. Two times difference in symbol.gridSize makes everything two times larger or smaller. Even if text sizes are set in the .qeda.yaml in mm (as documentation says) they are affected by gridSize parameter.

Second: gridSize is seems to be not a multiplier, but a divider. And this is very counter-intuitive. Default gridSize sets pin spacing to 2.54 mm (documentation says it's 2.5 mm which is untrue), the same is when gridSize is 2.54.
But gridSize 5.08 actually sets pin spacing to 1.27 mm. And gridSize 1.27 sets pin spacing to 5.08 mm.

Third: Font sizes are tied to symbol.gridSize wrongly.
fontSize 2.54 gives the following font height:
when gridSize is 2.54 (default) it is 1.27 mm
when gridSize is 1.27 it is 2.54
when gridSize is 0.635 it is 5.08
when gridSize is 5.08 it is 0.635
If fontSize is tied to gridSize it would be actually logical for it to be tied to default gridSize.

Fourth: Pin length is hard tied to gridSize (or at least documentation says so).
Setting gridSize to 1.27 allows me to get 5.08 mm pin spacing, but pins are 10.16 mm long and there is no way to affect it.

Suggestions:

1. Make symbol.gridSize a size multiplier, i.e. make it to be proportional to pin spacing.
2. Update documentation to reflect fontSize dependency on gridSize OR make then independent.
3. Add symbol.pinLength parameter or describe it in documentation if it actually exists.

I want to split 144-pin component to separate domains, because all 144-pin IC symbol does not fit on page.
For example stm32f429z.
I want split it to 3 parts: POWER (vcc+vss), LTDC, GPIO
problem with domain GPIO - how can I select pins, that does not included in LTDC?

There are still many chapters in the documentation that contain only text 'To be written.'. Are you planning to write them? Especially land patterns need documentation i think because it's not obvious how to use them.

Reference designator in IC schematic symbol requires more space (for long RefDes, e.g. U689).

A dfn.coffee file is missing from this folder: qeda/src/pattern/default/
I guess it should contain the followings:

twoPin = require './common/two-pin'

module.exports = (pattern, element) ->
  housing = element.housing
  housing.dfn = true
  twoPin pattern, element

Many parts (QFN, SON) often has a Tab with a 45° cut corner for signing pin 1 position. It would be nice to be able to define a tabCut parameter, which tells the cut distance from the corner.

Добрый день!
Огромное спасибо за вашу работу, это именно то, что, по-моему личному мнению, все сообщество ждало многие годы!

Попробовав ваше приложение я столкнулся с нехваткой генерации переменного резистора. Я далеко не программист, но попытался добавить этот функционал в файл ..\qeda\lib\symbol\default\resistor.js

Вышло сносно, можно ли Вас попросить добавить этот функционал в мастер ветку?

Файл прилагаю (прошу прощения за такой способ, я еще не освоил работу с github)
resistor.js.txt

С пребольшим Уважением к Вам и Вашей работе в сфере открытого ПО.

Hi Shamil,

Your README file doesn't provide any way to contact you, to get your email i had to clone qeda repo and check the logs.

I think you should add contact information to your README and as well to your qeda.org website.

1. I'm trying library element 'irf/irf4905s.yaml', but symbol is generated without pins

1. Can I use FET-symbol in multipart element, such as IRF7313 - dual N-FETs?

PS. qeda version is 0.2.4

Add symbol.groupGap parameter which allows to change the gap between pin groups in schematic symbol drawing. The gap is measured in grid cells.

When I generate BGA land patterns with collapsing ball (or NSMD pads), I would like to define custom values for the solder mask and paste margins.
For example typical values for a 0.4 pitch WLCSP (BGA):

• Pad: ⌀0.240 mm
• Solder mask: ⌀0.320 mm
• Stencil opening: ⌀0.280 mm

In a .kicad_mod file such a pad definition looks like this:

  (pad A1 smd circle (at -0.8 0.6) (size 0.24 0.24) (layers F.Cu F.Paste F.Mask)
    (solder_mask_margin 0.04) (solder_paste_margin 0.02))

So, I propose to have solderMaskMargin and solderPasteMargin parameters for BGA pad definitions, and also for custom pads (or wherever it would be useful).

More info about the optimal BGA land patterns for WLCSP packages:
http://www.nxp.com/documents/application_note/AN10439.pdf
http://www.ti.com/lit/an/snva009ag/snva009ag.pdf