parallella / parallella-hw Goto Github PK

Issue:
-If the 5V DC power is removed while while keeping the USB peripheral connector (J6) connected to a non-conforming powered USB hub, the USB port will eventually get "burned" rendering the USB port non-operational.

Why it happens:
-When the 5V DC connector is removed, the SYS_5P0V signal drops to 3.9V which is just enough to allow the Intersil regulators to stay up.
-Since the rails stay up there is no reset triggered and the EN signal for the bidirectional switch (U13) stays up allowing significant current to flow back from the VBUS to SYS_5P0V keeping the circuit powered.
-The U13 circuit and the rest of this path was not designed to draw 1A+, so eventually the circuit gets fried.

Potential Immediate Workarounds:

RECOMMENDED:
-Connect a powered USB hub and Parallella to a common power strip to power both devices on/off at the same time.(tested)

OTHER OPTIONS:
-Only use un-powered USB hubs(tested)
-Use a conforming USB powered hub that prevents power flowing back to the Parallella board(untested)
-Modify the USB cable to the powered hub to remove the VBUS line(untested)
-Modify a USB cable to put a low forward-voltage-drop diode on USB VBUS line, preventing current from flowing back.(untested)

Long Term Fixes:
-We are working on a bullet proof board fix for to be implemented as soon as possible but we will not hold up production.

The forum thread can be found here:
http://forums.parallella.org/viewtopic.php?f=10&t=841

Currently the elink frequency is not running at full speed. After we have the Vivado project released, the next step will be to push the elink transmit frequency to 500Mz (ie 1GB/s downstream bandwidth to the Epiphany).

Tasks needed:
-instantiate a DMA master engine on the PL to pull data from DRAM and deposit on the elink
-create driver layer to enable using the dma with p_read/p_write
-optimize axi interfaces to work for 1GB/s throughput
-push the tx_lclk/lvds_serdes frequency to 500MHz (synthesis+place and route not trivial...)

Of course in order to have a proper open source elink we also need a proper open source DV environment. Here is the one that we used to verify the Epiphany chips. (GPL license)

Since the Epiphany and the elink are both based around the same 104 bit interface with 32 bit addresses, it should be possible to create an environment that takes care of this...in fact as I write this I am realizing that I can contribute one of the chip environments to the parallella-hw as a starting point.

https://github.com/adapteva/epiphany-dv

Hi,

I was revisiting adding FuseSoC support for parallella and all its support cores and noticed the refactoring of the repo. It would be great to split out the RTL files to a separate (epiphany-rtl? parallella-rtl?) repo for several reasons. It would make it easier for non-parallella boards to reuse the Epiphany-facing RTL and it will save users from pulling in all the Kicad files, old prototype board projects and other things.

Now would probably be a good time as most people probably still haven't updated after the refactoring. If you want a unified repo this could still be managed by importing the RTL repo as a git submodule

Hello every:
I bought a P1601 and according the "Quick Start Guide" to do it. But I do not know the ip of P1601, so I can not login it. I used "Ubuntu 15.04 Headless Without Epiphany Support" SDcard image, so there is no screen display.
Who can tell me the default IP?
Thanks.

Following the Readme in fpga/projects/parallella_7020_headless on a Ubuntu 14.04 with PlanAhead 14.7 the bitstream generation failed with 14 critical warnings and two errors.

First I got:

[Netlist 29-73] Incorrect value '10.000000' specified for property 'CLKIN1_PERIOD'. The system will either use the default value or the property value will be dropped. Verify your source files. ["/home/marvin/Development/parallella-hw/fpga/projects/parallella_7020_headless/parallella_7020_headless.runs/synth_1/parallella_z7_top.ngc":70359]

and for CLKIN2_PERIOD the same but with the value '0.000000'. These both result in the following error for the ngdbuild task:

ERROR:LIT:374 - Attribute CLKIN1_PERIOD on MMCME2_ADV instance
"parallella/ewrapper_link_top/io_clock_gen/mmcm_adv_inst" has invalid value
"0,000000". The CLKIN1_PERIOD attribute should have a real number, followed
by optional time or frequency units; nS are assumed if no units are given.

The same error will occur also for CLKIN2_PERIOD. This point is interesting because in io_clock_gen_600mhz.v is only a definition for CLKIN1_PERIOD and no definition for CLKIN2_PERIOD. Also the value set for CLKIN1_PERIOD with '(10.0)' looks correct (according to the Xilinx documentation).

As you can see the comment for CORE_GENERATION_INFO in this file, there was an earlier version where a CLKIN2_PERIOD with value 10.0.

Searching for CLKIN2_ in an clean git clone of the projects found some files, interestingly none with the value 0.0. According to the Xilinx docu xco-files are only logfiles and should not parsed by the build process.

The other files that contains CLKIN2_ come from external IP cores in the folder /fpga/externals/fpgahdl_xilinx/motor_control/. I assume that these files are not relevant for the project, or?

I've tried to delete the xco-files with no effect. Another try to add the definition of CLKIN2_PERIOD also has no effect, still same errors occur.

In conclusion it looks as some definitions of the zynq in the Xilinx toolchain differ from others. So while the implementation processes run the settings in the project will be overwritten.

Hi,
Is there some plan to manufacture the next batch of Parallella Embedded board? I did not find any e-shop where Parallella embedded is in the stock.
Digikey marks the Parallella Embedded version as "Not Recommended for New Design" .

In buddy/docs. (Also would be nice to have the generated buddy_reference.pdf in there.)

The current saxi interface contains two auto generated files from Vivado. This needs to be cleaned up eventually. Only one level of hierarchy needed (remove wrapper)

I've tried the parallella_e16_headless_gpiose_7020.bit.bin bitstream and the system is not coming up. I renamed it and replaced the original file at the boot partition. According to the Xilinx documentation the bitstream size for an 7020 should be 4045564 bytes. The original bitstream from feb. has this size.

Do I have to change some other configurations?

The current headless archive is correct logically, but is not suitable for maintenance going forward. I a have re-factored the code and made slight modifications (nothing "should" break the design")...
The entry point can be found here.
"fpga/src/elink/hdl/elink.v"

Work to be done. Help appreciated (in Vivado 2014.3):

Step 1: Create a reusable Vivado IP block out of the elink

Step 2: Update the verification environment to instantiate the new elink IP block

Step 3: Create a top level project for the headless design (elink+clocks+gpio+reset+pin assignment)

Trying to follow instructions here. Need to generate ps7_init_gpl.c somehow

https://www.parallella.org/2015/03/23/new-parallella-elink-fpga-design-project-now-available-in-vivado/

This link is wrong:
https://raw.github.com/parallella/parallella-hw/master/fpga/archives/parallella_7020_headless.xpr.zip
should be:
https://raw.github.com/parallella/parallella-hw/master/fpga/vivado/archives/parallella_7020_headless.xpr.zip

When I open the project I get these warnings. (just annoying)

open_project /tmp/parallella_7020_headless_gpiose_elink2/parallella_7020_headless_gpiose_elink2.xpr
[Project 1-311] Could not find the file '/tmp/parallella_7020_headless_gpiose_elink2/parallella_7020_headless_gpiose_elink2.srcs/sources_1/bd/elink_testbench/ip/elink_testbench_elink_gold_0_1/elink_testbench_elink_gold_0_1.upgrade_log', nor could it be found using path '/home/frhuettig/.Xil/Vivado-3130-FredsLaptop/PrjAr/_X_/parallella_7020_headless_gpiose_elink2.srcs/sources_1/bd/elink_testbench/ip/elink_testbench_elink_gold_0_1/elink_testbench_elink_gold_0_1.upgrade_log'.
[Project 1-311] Could not find the file '/tmp/parallella_7020_headless_gpiose_elink2/parallella_7020_headless_gpiose_elink2.srcs/sources_1/bd/elink_testbench/ip/elink_testbench_eio_tx_0_0/elink_testbench_eio_tx_0_0.upgrade_log', nor could it be found using path '/home/frhuettig/.Xil/Vivado-3130-FredsLaptop/PrjAr/_X_/parallella_7020_headless_gpiose_elink2.srcs/sources_1/bd/elink_testbench/ip/elink_testbench_eio_tx_0_0/elink_testbench_eio_tx_0_0.upgrade_log'.
[Project 1-311] Could not find the file '/tmp/parallella_7020_headless_gpiose_elink2/parallella_7020_headless_gpiose_elink2.srcs/sources_1/bd/elink_testbench/ip/elink_testbench_eCfg_0_2/elink_testbench_eCfg_0_2.upgrade_log', nor could it be found using path '/home/frhuettig/.Xil/Vivado-3130-FredsLaptop/PrjAr/_X_/parallella_7020_headless_gpiose_elink2.srcs/sources_1/bd/elink_testbench/ip/elink_testbench_eCfg_0_2/elink_testbench_eCfg_0_2.upgrade_log'.

STEP 4: Run Synthesis

launch_runs synth_1
[BD 41-1336] One or more IPs are locked in this design 'elink2_top.bd'. Please run report_ip_status for more details and recommendations on how to fix this issue.
[BD 41-1336] One or more IPs are locked in this design 'elink2_top.bd'. Please run report_ip_status for more details and recommendations on how to fix this issue.
Synthesis[Synth 8-439] module 'elink2_top' not found ["/tmp/parallella_7020_headless_gpiose_elink2/parallella_7020_headless_gpiose_elink2.srcs/sources_1/bd/elink2_top/hdl/elink2_top_wrapper.v":159]
[Synth 8-285] failed synthesizing module 'elink2_top_wrapper' ["/tmp/parallella_7020_headless_gpiose_elink2/parallella_7020_headless_gpiose_elink2.srcs/sources_1/bd/elink2_top/hdl/elink2_top_wrapper.v":12]
[Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

In parallella_7020_hdmi:
XPS > Clock Generation > PL Fabric Clocks > FCLK_CLK1 is set to 152.
I changed it to 125.

In parallella_7010_hdmi, parallella_7020_hdmi:
XPS > Bus Interfaces > clock_generator_0 > (right click) > Configure IP > CLKIN: Input Clock Frequency: 0 (changed to 100000000)

CLKOUT0: Required Frequency: 0 (changed to 12288135)

On page 6 in generation 0 and page 7 in generation 1, a sentence in the parallella reference reads "The Parallella-64 board includes the 64-cire Epiphany-IV processor"

The current test environment is quite primitive. It works with a set of golden vectors in a tabular text format.

Example:
pal/src/math/test/p_log10_f32.dat

Currently some of the functions are missing test vectors, and certainly all functions need more exhaustive testing...open to suggestions with respect to framework. (I am sure there is a lot out there).

I have had great success with plain text based unit testing in the past. (at least as an intermediate format).

The current pal/src/test_main.c is VERY primitive. What I would prefer not having is a personalized test function for each function that is copy pasted or auto generated by some other program (been there done that...) Since all of the functions are quite similar and math oriented, it seems that a common single test framework with input data and expected data is the way to go?

Currently the path from Epiphany to FPGA is limited to 150MHz. The current FPGA design meets timing at 300MHz, but we still have some validation needed to get it there. For now it seems that most chips work fine at 300MHz if we bump up the core voltage to 1.1V.

We need help validating this voltage bump workaround and getting to the root cause of this problem.

To modify voltage, use this script:
https://github.com/parallella/parallella-utils/tree/master/power_management

The board will become unstable under unless cooled properly. In order of preference, here are some methods for lowering the operating temperature in order of effectiveness.

-Use any type of fan, a gentle breeze should do (most effective)
-Install the heatsink on the zynq
-Install a second heatsink on epiphany
-Put the board on its side to improve natural convection (least effective)

A discussion can be found here:
http://forums.parallella.org/viewtopic.php?f=10&t=849

Clearly heat dissipation is always going to be a challenge for such a small and packed board and we will continue to update this issue as we improve the solutions. 5 Watts is simply too much for a credit card sized board without aggressive thermal counter measures.

The uUSB and uHDMi connectors can come loose, given moderate force.

The thread illustrating the issue can be found here:
http://forums.parallella.org/viewtopic.php?f=10&t=853

The fpga/edk/parallella_7020_hdmi/system.xml search path for ip-cores is based under /mnt/windowsC … Therefor the generating of the Netlist will failing.

Additionally the clock settings for C_FCLK_CLK<#>_FREQ differ from the general settings in the system.mhs file.

Good Evening!

I am trying to look at the PCB layout files for your parallella FPGA. The link resolves to a 404 error. Would you be able to restore this resource?

Thanks,
Matthew Matusek

SHA: a826fbb

In parallella-hw/fpga/vivado_projects/parallella_7020_headless/parallella_7020_headless.tcl,
lines 97-127 point to a non-existent directory $origin_dir/../../hdl

It looks like some of the original directory tree still exists in parallella/hw-fpga/old and most of the Verilog source files have been moved to the ../../src directory, but the files in the ./parallella-I sub-directory appear to be missing in the new file structure.

The current maxi interface contains two auto generated files from Vivado. This needs to be cleaned up eventually. Only one level of hierarchy needed (remove wrapper)

Now that the new elink is working, we need to integrate the block with the HDMI controller from ADI.

Step1: Run through the ADI wiki and generate a bit-stream
Entry point:
http://wiki.analog.com/resources/fpga/docs/hdl#building_on_vivado

Step2: Test bitstream with current linux kernel (with Epiphany disabled i kernel) to make sure linux boots and we have a complete system.

Step 3. Create a new top level project that includes the elink IP block and ADI's hdmi design to complete integration. Create bit stream, test, release...

During refactoring, instantiations of fifo_async_103x32 was replaced with fifo_async_emesh, but no such file exists in the repo

The Porcupine (1 and 2) include connectors for the elink that have been shown to work, but the interface is still considered to be in the "lab" phase. There is a whole lot of IO goodness sitting there right now waiting to be used, but the feature needs broader validation before being released as a product. Some things to try.

1.) How fast can you drive the signals by setting bits on the north south interface in software?
(see Table 2)
http://www.adapteva.com/docs/e16g301_datasheet.pdf
This effectively gives you access to another 16 high speed differential outputs.

2.) Hooking up the North and South connector and doing loop-back testing. You will need to set the loop-back mode in Table 2 of the datasheet.

Create a clean elink design that is completely free of binary IP. We did this with the first design of the elink 3 years ago, but due to performance reasons we had to moved towards using FPGA IP. It would be fantastic to have a truly portable clean implementation of the elink that is not reliant on the vendor specific IP.

Suggestion is to use `define TARGET_OPEN as the keyword. The blocks that need to be implemented include:

single ported memory
dual ported memory
sync fifo
async fifo
serdes for rx and tx

The current auto generated binary blob bram controller needs to be replaced with a clean open source design.

The interface of emmu.v seems to have been changed since dv_emmu was written. I tried to do some simple renaming, but there seem to be more changes needed

Hello, I was looking at your board on your website and I can not see any pin outs, specs on them, etc. Nor can I see and USB connectors. Is parallella really a connection-less board excepting the Ethernet?

I am attempted to get a PCB printed. However, I am having difficulty with the current Kicad project file and gerber files. I am unable to produce the files in a format that I can submit for printing.

Would it be possible to provide the files in a format that they could be accepted by a PCB manufacturer, like OSH Park?

Very Respectfully.