Comments (2)
Please read the comments in the project directory (README), it's explained there. I've seen this before with Xilinx they are not friendly to moving things around, i.e. relative paths. I tried explicitly setting a relative path for the ip-cores but it didn't work. Any suggestions welcome.
I'll look into the frequency question, I have not seen any warnings about that. Thanks.
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Thnx, I haven't noticed this Readme before.
The clock problem occurs also at the non HDMI project.
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Related Issues (20)
- HDMI not working with new elink design
- Release refactored elink project HOT 2
- Clean up AXI maxi interface HOT 1
- Clean up AXI slave interface HOT 1
- Replace axi_bram_ctrl with Verilog open source axi slave interface HOT 1
- A clean "no-ip" version of elink HOT 10
- A verilator/systemC based test bench for "no IP" based elink HOT 1
- Increase elink data rate (FPGA-->epiphany)
- Increase elink data rate (epiphany-->FPGA) HOT 1
- Improve math test environment and vectors HOT 1
- Porcupine elink connector validation
- fifo_async_emesh is missing HOT 1
- Synthesis fails HOT 1
- Porcupine PCB Printing Issue HOT 4
- Pinouts USB? HOT 1
- the IP address of P1601 HOT 2
- Parallella Embedded (P1602) out of stock
- Missing buddy_reference.md
- .
- parallella_layout.brd 404 Error
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