Comments (5)
Nice sleuthing!
Indeed, this won't speed up actual circuits, because constructing a structure in Verilog doesn't cost anything (it just means remembering that a bunch of wires are bundled together).
On the simulation side it's a nice speedup, but we don't really want to "cheat" by rewriting code to make the simulator happier (especially because these sort of code changes then make it harder to say anything sinceere about Cuttlesim vs. other simulators, since we would have modified the code to fit Cuttlesim better). Instead, we should improve the simulator so that it handles this pattern better (It's a common pattern in the bluespec world).
I thought I did some experiments with this in the past, but I can't find my notes about them. What happens to performance if you force inlining of that function call at the C++ level (IIRC __attribute__((always_inline))
should do it)? Ideally inlining + dead code elimination should get rid of the unnecessary computation.
If that doesn't work, or if it's unreliable, then this would be a really interesting optimization pass to implement in Cuttlesim! We would check whether a function is pure and returns a struct, and if it does we would inline just the relevant computations. Sounds fun, actually :)
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I just took a glance at how the C++ code for getFields
is generated. As it is not a rule but a function, it returns by modifying its ret
argument (initially passed by reference). This argument refers to a temporary variable created by the CALL_FN
macro in the surrounding statement expression. Just a quick heads up, I guess that naming something tmp
in a Kôika function (which should not be too rare) could lead to frustration since it would be hidden by this variable when used as an argument. This is especially true in the case where an element of type T
called tmp
is passed to a function returning T
, since then the compiler wouldn't even complain about types not matching.
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Great catch, thanks! Fortunately, there's at least an inkling of the issue thanks to the compiler printing a warning (cuttlesim.hpp:253:47: warning: ‘tmp’ may be used uninitialized in this function [-Wmaybe-uninitialized]
).
I pushed a fix just now.
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An occurrence of tmp
was left unchanged in the READ
macro, which leads to errors when compiling anything that uses it (e.g. examples/conflicts_modular.v
: cuttlesim.hpp:1403:27: error: ‘tmp’ was not declared in this scope; did you mean ‘tm’?
).
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Ugh, thanks a lot!
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Related Issues (20)
- Building error (Ocaml 4.11.1) HOT 10
- About the upcoming module system and Kôika's semantics HOT 1
- `unit_t` in ext_fn_t input generates invalid verliog HOT 8
- External function incorrectly pruned if rule is otherwise uneffectful HOT 3
- Context unknown during type checking HOT 2
- Different behavior in simulation and FPGA HOT 3
- Avoidable stalling in the RISC-V example HOT 2
- Multiplier correctness example HOT 1
- Build issues on macOS HOT 26
- Some circuits that include extcalls behave unexpectedly when simulated through Verilator HOT 3
- Infinite loop HOT 4
- Translating Koika's bits_t (Vect) to MIT's bbv HOT 1
- Compilation error with the cosimulation example when verilator >= 5.004
- Vectors and name collisions HOT 2
- "make verilator-tests" results in a failure (cannot find file containing module: 'ext_host_id') HOT 2
- Outdated information in examples/rv/README.rst HOT 8
- Errors in examples/rv/MultiplierCorrectness.v HOT 2
- Proof failures with (unsupported) Coq 8.12 HOT 3
- Warning message about Boost version triggers spuriously HOT 1
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