Comments (3)
I might be approaching this wrong, but my problem is that my Koika design will be part of a larger design, and the larger design is not combinational. To get signals in/out of my design I have been using external functions with efr_internal := false to expose input output signals in the verilog interface - perhaps there is another way to achieve this?
You're doing it right, but it requires extra care because Kôika doesn't have a good story about its module system at the moment. I summarized this in #2 (comment) , and there are more details about this in #10 ; the first link in particular has a pretty detailed description of how to do this safely (the main example we have of this is the bus in the RISCV core. If you want me to look at a concrete case I'll be happy to give design-specific advice.
from koika.
This is correct behavior, although it can be unexpected: functions are specified to be pure (they need to have a pure model), so if their return value is unused they can be eliminated.
The trick to force them to be kept is to use the return value, e.g. by writing it to a dummy register, as you noticed.
I don't understand your second example too well — what is it about the nonconstant value?
(This will be fixed when we have proper support for modules, since function calls will become observable and hence not tivially optimizable)
from koika.
This is correct behavior, although it can be unexpected: functions are specified to be pure (they need to have a pure model), so if their return value is unused they can be eliminated.
I might be approaching this wrong, but my problem is that my Koika design will be part of a larger design, and the larger design is not combinational. To get signals in/out of my design I have been using external functions with efr_internal := false
to expose input output signals in the verilog interface - perhaps there is another way to achieve this?
I don't understand your second example too well — what is it about the nonconstant value?
I just noticed that the external call was dropped with write0 (dummy, Ob~0)
but not with write0 (dummy, previous_total)
, (still_dropped
not mentioned in either).
from koika.
Related Issues (20)
- Building error (Ocaml 4.11.1) HOT 10
- About the upcoming module system and Kôika's semantics HOT 1
- `unit_t` in ext_fn_t input generates invalid verliog HOT 8
- Context unknown during type checking HOT 2
- Different behavior in simulation and FPGA HOT 3
- Avoidable stalling in the RISC-V example HOT 2
- Potential optimization in the RISC-V example HOT 5
- Multiplier correctness example HOT 1
- Build issues on macOS HOT 26
- Some circuits that include extcalls behave unexpectedly when simulated through Verilator HOT 3
- Infinite loop HOT 4
- Translating Koika's bits_t (Vect) to MIT's bbv HOT 1
- Compilation error with the cosimulation example when verilator >= 5.004
- Vectors and name collisions HOT 2
- "make verilator-tests" results in a failure (cannot find file containing module: 'ext_host_id') HOT 2
- Outdated information in examples/rv/README.rst HOT 8
- Errors in examples/rv/MultiplierCorrectness.v HOT 2
- Proof failures with (unsupported) Coq 8.12 HOT 3
- Warning message about Boost version triggers spuriously HOT 1
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