Avoidable stalling in the RISC-V example about koika HOT 2 OPEN

Good stuff! :) Looping in @threonorm , who wrote the code; I wonder if the same pattern existed in the Bluespec version of the code.

This results in tests taking roughly 25% less time with Cuttlesim and 5% less time for Verilator.

I like this change ^^

from koika.

Yes, we currently stall conservatively for source register (but do not add dependencies for destination registers which are not real destinations). Mainly because the design we started from was doing that (it is coming from a class).

I don't have a strong opinion, we can merge that change as it is not important to keep the comparison with the baseline anymore.

Here are the things I think we should look at:
1 - variations on the number of cycles (instead of simulation time, that can vary quite a bit and is not really architecturally meaningful)
2 - variation on the critical path both on FPGA and the open pdk synthesis
3 - variation on the type checking + compilation time
(4 - incompatibilities/porting work/variations on the symbolic evaluation time/use in already written proofs)

Maybe we can do a little experimentation for 1) and 2), I think the critical path is currently in decode on the equivalent pattern for the destination register and the scoreboard. Or at least that's what I remember, so it may move to go to the source instead, not sure.

For 3), hopefully it should not influence too much, but we have seen weirdness before, so it could be good to confirm it.

I think for 4), this could impact the proof we did for the enclave system, but we probably don't want to keep the code in sync anyway (and it is probably out of sync already), so I don't mind ignoring that dimension.

I can look at 1, 2, 3 but sadly not before august.

from koika.