the include and the imports should be moved inside the interface

Parameters used
Number of lanes 16
Max pipe width 32
pipe width 8
Dut is downstream

clock period is 2 time-units

steps :
-TxDetectRxloopback received =1 at 17 timeunit
-PhyStatus asserted at 19 timeunit
-RxStatus = 3'b011 at 19 timeunit (Receiver detected)
-PhyStatus de-asserted after 1 clock cycle at 21 timeunit
-RxStatus = 3'b000 after 1 clock cycle at 21 timeunit
-Here we are expecting powedown to be P0 to start sending TSs in polling state

These signals must be per-lane not a shared signal

• PCLKChangeOK
• PCLKChangeAck

• move the "pipe_data_width_e" to the pipe_agent_pkg
• change the structs to become typedefs (tlp_t, dllp_t)

modify to use the 2 analysis ports

• make 2 analysis ports instead of 1 (refer to connections section in the doc)
• in the build_phase you are setting a variable inside the driver before instantiating the driver
• the line of "ap = lpif_monitor_h.ap;" should be replaced with a line that connects the 2 analysis ports of the monitor to the 2 analysis ports of the agent
• and also connect the 2 analysis ports of monitor to the coverage monitor

• which device does postCursorCoefficient represent?

• Makefile Comments
• Compilation -> Simulation
• Sequences -> driver/monitor_bfm (Send seq item to the driver)
• Add uvm_infos
• Reviewing the spec document
• Add proxy variables
• Implement top modules
• Print topology, factory, config in connect_phase in pcie_test
• Parameterize the interfaces and use localparams
• add sequences comma separated in Makefile
• Make a time plan

• The code compiles
• The questions document (Today)
• Apply guidelines

Parameters used
Number of lanes 16
Max pipe width 32
pipe width 8
Dut is downstream

clock period is 2 time-units

steps :
-TxDetectRxloopback received =1 at 17 timeunit
-PhyStatus asserted at 19 timeunit
-RxStatus = 3'b011 at 19 timeunit (Receiver detected)
-PhyStatus de-asserted after 1 clock cycle at 21 timeunit
-RxStatus = 3'b000 after 1 clock cycle at 21 timeunit
-At 23 timeunit , TxDetectRxloopback was asserted again which was not expected

The signal should be asserted in detect state ( Receiver Detetction Scenario)

• " Lpif_agent_config lpif_agent_config_h; " the "Lpif" should be "lpif"
• "lpif_monitor_bfm_h = lpif_agent_config_h.lpif_monitor_bfm_h; " and "lpif_monitor_bfm_h.lpif_monitor_proxy = this;" should be moved to the connect_phase function
• "lpifseq_item_f.lpif_operation=LINK_UP;" "lpifseq_item_f" should be "lpif_seq_item_f"
• the functions outside the class should be all without indentation

we forgot to talk about this package in the last meeting. can you implement this package since it is related to your task? it won't take any time from you

Parameters used
Number of lanes 16
Max pipe width 32
pipe width 8
Dut is downstream

clock period is 2 time-units

steps :
lpif side:
-lpif reset =0 (asserted) at 1 timeunit
-lp_state_req= 4'b0000 (Reset) at 1 timeunit
-lpif reset =1 (de-asserted) after 1 clock cycle (at 3 timeunit)

pipe side:
-phy reset received =0 at 1 timeunit
-Here we are expecting TxEelecidle to be asserted
-phystatus asserted at 1 timeunit
-phy reset received =1 after 1 clock cycle (at 3 timeunit)
-phystatus de-asserted at 5 timeunit

• lpif reset and link up
• clock generation in hdl top
• finishing the pipe monitor bfm
• finish the equalization
• create a randomized var for determining if downstream or upstream or get its value from the command line
• make instance of the DUT and connect it to the env interfaces
• modify the makefile to compile the design files
• starting from thursday 3/6 commits should be done only with issues
• hdl.f file for the names of the files to be compiled (look in the user manual of questasim to find the flag-f for vlog command)

Parameters used
Number of lanes 16
Max pipe width 32
pipe width 8
Dut is downstream

clock period is 2 time-units

steps :
lpif side:
-lpif reset =0 (asserted) at 1 timeunit
-lp_state_req= 4'b0000 (Reset) at 1 timeunit
-lpif reset =1 (de-asserted) after 1 clock cycle (at 3 timeunit)

pipe side:
-phy reset received =0 at 1 timeunit
-Here we are expecting powerdown to be P1 and TxEelecidle to be asserted
-phystatus asserted at 1 timeunit
-phy reset received =1 after 1 clock cycle (at 3 timeunit)
-phystatus de-asserted at 5 timeunit
-Here we are expecting powerdown to be P1 (in detect state)

                         - 

• it should contain 2 analysis ports instead of 1 (refer to the connections section in the document)
• it won't get the agent configuration object from the db. the config object will be set from the agent
• the logic of setting the monitor_bfm should be moved to the connect_phase
• the "proxy" variable inside the monitor_bfm should be also set in the connect_phase after setting the monitor_bfm var

In BFMs we need to wait for a signal from the env. this could be done easily with wait but wait is not synthesizable. we can make the bfm as a fsm so it will be synthesizable. so what method should we use?

• Equalization Signals
• Signal list from specs and compare it to the design specs and create a table in the DUT Verification document (Signal name, direction, Signal Description, Comment of why it remains/removed)
• Finish scenario walkthrough
• Finish sequences, drivers, monitors
• Finish Link Up
• Adjust the sequences, drivers, drivers_bfm, monitors, monitors_bfm, configuration objects and sequence items to the new abstraction level
• Adjust the parameterization and local_params to put the local_params in the parameters list

• there is no need for the handles of the config objects since they will be declared and used in the build_phase
• "spi_test_base::new" "spi_test_base" is used multiple times and it should be "pcie_test"
• "virtual intr_bfm temp_intr_bfm;" why do we need this?
• the scope of the pcie_env config object in the db should be set to the env only not to "*"
• In the run_phase, the value of "+VSEQ=" will be multiple names of virtual sequences separated by commas (e.g: "+VSEQ=vseq1,vseq2,vseq3") so the logic of splitting the virtual sequences and looping over all the virtual sequences is missing
• in run_phase, I think instead of declaring the "vseq" variable multiple times depending on the chosen virtual sequence, you can declare it once as "uvm_sequence#(uvm_sequence_item)" and set the value depending on the chosen virtual sequence
• the logic of raising and droping objections is missing in the run_phase

• modify the names and the values of the enums to follow the convention and to have the needed values

For each package file there will be a .mk file with the same name. This .mk file will be responsible for compiling this specific package.
The main MakeFile will include all the .mk files and calls them

Example for pipe_agent_pkg

INCLUDE_DIR          := ../../
FILES                := pipe_if.sv pipe_agent_pkg.sv pipe_driver_bfm.sv pipe_monitor_bfm.sv

pipe_build:
	vlog +incdir+${INCLUDE_DIR} ${FILES} -suppress 2275 -suppress 2286

clean:
	rm -r work

# 2275 --> warning for file already included and will be overwritten 
# 2286 --> Using implicit +incdir+C:/questasim64_10.4e/uvm-1.1d/../verilog_src/uvm-1.1d/src 
#						from import uvm_pkg

Compile output is:

$ make -f pipe_agent.mk
vlog +incdir+../.. pipe_if.sv pipe_agent_pkg.sv pipe_driver_bfm.sv pipe_monitor_bfm.sv  -suppress 2275 -suppress 2286
QuestaSim-64 vlog 10.4e Compiler 2016.04 Apr  9 2016
Start time: 15:08:10 on Feb 06,2021
vlog "+incdir+../.." pipe_if.sv pipe_agent_pkg.sv pipe_driver_bfm.sv pipe_monitor_bfm.sv -suppress 2275 -suppress 2286
-- Compiling package common_pkg
-- Compiling interface pipe_if
-- Importing package common_pkg
-- Compiling package common_pkg
-- Compiling package pipe_agent_pkg
-- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in)
-- Compiling interface pipe_driver_bfm
-- Importing package pipe_agent_pkg
-- Compiling interface pipe_monitor_bfm

Top level modules:
        --none--
End time: 15:08:11 on Feb 06,2021, Elapsed time: 0:00:01
Errors: 0, Warnings: 0, Suppressed Warnings: 1

Is this mechanism ok or not?

• the parameter name of the "write" function should be changed to match the document
• everything inside the class should be indented

• 2 analysis ports needed instead of 1
• the pipe_agent_config handles inside the driver and the monitors need to be set in the build_phase
• the logic of setting the virtual interfaces of driver_bfm and monitor_bfm will be moved to the connect_phase inside these components
• change begin/end to follow the convention
• the pipe_agent configuration object's name in the uvm_config_db is "pipe_agent_config_h" instead of "pipe_config_db"
• the name of the first parameter of the constructor should be the name of the variable
• "pipe_monitor_h.ap.connect(this.ap);" no need for "this" here
• the logic of connecting the monitor's analysis ports to the coverage monitors' export is missing

• move setting the driver_bfm to the connect_phase instead of the build_phase
• in "pipe_seq_item seqitem;". the "seqitem" should be "pipe_seq_item_h" to follow the convention
• everything inside the class should be indented

LPIF

• What is pl_link_cfg used for ?
• What is meant by port in LPIF ?

PIPE

UVM

• Do we need to add a logic in monitor to check that the protocol is running correctly or just to sample the signals and create TLM objects ?!
• Are assertions used in interfaces lpif_if.sv and pipe_if.sv to check for protocol rules ?