PCIE 5.0 Graduation project (Verification Team)
To run the Environment:
- navigate to tb/sim
- run
make build
to build the environment - run
make run
to run the code
PCIE 5.0 Graduation project (Verification Team)
the include and the imports should be moved inside the interface
Parameters used
Number of lanes 16
Max pipe width 32
pipe width 8
Dut is downstream
clock period is 2 time-units
steps :
-TxDetectRxloopback received =1 at 17 timeunit
-PhyStatus asserted at 19 timeunit
-RxStatus = 3'b011 at 19 timeunit (Receiver detected)
-PhyStatus de-asserted after 1 clock cycle at 21 timeunit
-RxStatus = 3'b000 after 1 clock cycle at 21 timeunit
-Here we are expecting powedown to be P0 to start sending TSs in polling state
These signals must be per-lane not a shared signal
modify to use the 2 analysis ports
Parameters used
Number of lanes 16
Max pipe width 32
pipe width 8
Dut is downstream
clock period is 2 time-units
steps :
-TxDetectRxloopback received =1 at 17 timeunit
-PhyStatus asserted at 19 timeunit
-RxStatus = 3'b011 at 19 timeunit (Receiver detected)
-PhyStatus de-asserted after 1 clock cycle at 21 timeunit
-RxStatus = 3'b000 after 1 clock cycle at 21 timeunit
-At 23 timeunit , TxDetectRxloopback was asserted again which was not expected
The signal should be asserted in detect state ( Receiver Detetction Scenario)
we forgot to talk about this package in the last meeting. can you implement this package since it is related to your task? it won't take any time from you
Parameters used
Number of lanes 16
Max pipe width 32
pipe width 8
Dut is downstream
clock period is 2 time-units
steps :
lpif side:
-lpif reset =0 (asserted) at 1 timeunit
-lp_state_req= 4'b0000 (Reset) at 1 timeunit
-lpif reset =1 (de-asserted) after 1 clock cycle (at 3 timeunit)
pipe side:
-phy reset received =0 at 1 timeunit
-Here we are expecting TxEelecidle to be asserted
-phystatus asserted at 1 timeunit
-phy reset received =1 after 1 clock cycle (at 3 timeunit)
-phystatus de-asserted at 5 timeunit
Parameters used
Number of lanes 16
Max pipe width 32
pipe width 8
Dut is downstream
clock period is 2 time-units
steps :
lpif side:
-lpif reset =0 (asserted) at 1 timeunit
-lp_state_req= 4'b0000 (Reset) at 1 timeunit
-lpif reset =1 (de-asserted) after 1 clock cycle (at 3 timeunit)
pipe side:
-phy reset received =0 at 1 timeunit
-Here we are expecting powerdown to be P1 and TxEelecidle to be asserted
-phystatus asserted at 1 timeunit
-phy reset received =1 after 1 clock cycle (at 3 timeunit)
-phystatus de-asserted at 5 timeunit
-Here we are expecting powerdown to be P1 (in detect state)
-
In BFMs we need to wait for a signal from the env. this could be done easily with wait
but wait
is not synthesizable. we can make the bfm as a fsm so it will be synthesizable. so what method should we use?
For each package file there will be a .mk
file with the same name. This .mk
file will be responsible for compiling this specific package.
The main MakeFile will include all the .mk
files and calls them
Example for pipe_agent_pkg
INCLUDE_DIR := ../../
FILES := pipe_if.sv pipe_agent_pkg.sv pipe_driver_bfm.sv pipe_monitor_bfm.sv
pipe_build:
vlog +incdir+${INCLUDE_DIR} ${FILES} -suppress 2275 -suppress 2286
clean:
rm -r work
# 2275 --> warning for file already included and will be overwritten
# 2286 --> Using implicit +incdir+C:/questasim64_10.4e/uvm-1.1d/../verilog_src/uvm-1.1d/src
# from import uvm_pkg
Compile output is:
$ make -f pipe_agent.mk
vlog +incdir+../.. pipe_if.sv pipe_agent_pkg.sv pipe_driver_bfm.sv pipe_monitor_bfm.sv -suppress 2275 -suppress 2286
QuestaSim-64 vlog 10.4e Compiler 2016.04 Apr 9 2016
Start time: 15:08:10 on Feb 06,2021
vlog "+incdir+../.." pipe_if.sv pipe_agent_pkg.sv pipe_driver_bfm.sv pipe_monitor_bfm.sv -suppress 2275 -suppress 2286
-- Compiling package common_pkg
-- Compiling interface pipe_if
-- Importing package common_pkg
-- Compiling package common_pkg
-- Compiling package pipe_agent_pkg
-- Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in)
-- Compiling interface pipe_driver_bfm
-- Importing package pipe_agent_pkg
-- Compiling interface pipe_monitor_bfm
Top level modules:
--none--
End time: 15:08:11 on Feb 06,2021, Elapsed time: 0:00:01
Errors: 0, Warnings: 0, Suppressed Warnings: 1
Is this mechanism ok or not?
pl_link_cfg
used for ?port
in LPIF ?lpif_if.sv
and pipe_if.sv
to check for protocol rules ?A declarative, efficient, and flexible JavaScript library for building user interfaces.
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