@mas1998m
as you may know

• TxDetectRxLoopback is asserted in Detect.Active substate
• Detect.active substate is entered after waiting 12 ms in Detect.Quiet
• 12 ms timeout with Gen1 clock is about ~300000 cycle or more
• so please make sure that you are not at Detect.Quiet , and expecting TxDetectRxLoopback to be asserted
• if you are sure you are at Detect.Active , please specify the parameters you are working with to rerun the stimulus locally and check the problem

from pcie5_phy.

@NadaTarek-1 Please comment the final resolution before closing issues.

from pcie5_phy.

These are print statements we used to check the time. The clock period is 2 time units so the receiver detection should start at time ~1,500,000 time units but it didn't start

UVM_INFO @ 50000: reporter [hdl_top] Time: 50000

UVM_INFO @ 100000: reporter [hdl_top] Time: 100000

UVM_INFO @ 150000: reporter [hdl_top] Time: 150000

UVM_INFO @ 200000: reporter [hdl_top] Time: 200000

UVM_INFO @ 250000: reporter [hdl_top] Time: 250000

UVM_INFO @ 300000: reporter [hdl_top] Time: 300000

UVM_INFO @ 350000: reporter [hdl_top] Time: 350000

UVM_INFO @ 400000: reporter [hdl_top] Time: 400000

UVM_INFO @ 450000: reporter [hdl_top] Time: 450000

UVM_INFO @ 500000: reporter [hdl_top] Time: 500000

UVM_INFO @ 550000: reporter [hdl_top] Time: 550000

UVM_INFO @ 600000: reporter [hdl_top] Time: 600000

UVM_INFO @ 650000: reporter [hdl_top] Time: 650000

UVM_INFO @ 700000: reporter [hdl_top] Time: 700000

UVM_INFO @ 750000: reporter [hdl_top] Time: 750000

UVM_INFO @ 800000: reporter [hdl_top] Time: 800000

UVM_INFO @ 850000: reporter [hdl_top] Time: 850000

UVM_INFO @ 900000: reporter [hdl_top] Time: 900000

UVM_INFO @ 950000: reporter [hdl_top] Time: 950000

UVM_INFO @ 1000000: reporter [hdl_top] Time: 1000000

UVM_INFO @ 1050000: reporter [hdl_top] Time: 1050000

UVM_INFO @ 1100000: reporter [hdl_top] Time: 1100000

UVM_INFO @ 1150000: reporter [hdl_top] Time: 1150000

UVM_INFO @ 1200000: reporter [hdl_top] Time: 1200000

UVM_INFO @ 1250000: reporter [hdl_top] Time: 1250000

UVM_INFO @ 1300000: reporter [hdl_top] Time: 1300000

UVM_INFO @ 1350000: reporter [hdl_top] Time: 1350000

UVM_INFO @ 1400000: reporter [hdl_top] Time: 1400000

UVM_INFO @ 1450000: reporter [hdl_top] Time: 1450000

UVM_INFO @ 1500000: reporter [hdl_top] Time: 1500000

UVM_INFO @ 1550000: reporter [hdl_top] Time: 1550000

UVM_INFO @ 1600000: reporter [hdl_top] Time: 1600000

UVM_INFO @ 1650000: reporter [hdl_top] Time: 1650000

UVM_INFO @ 1700000: reporter [hdl_top] Time: 1700000

UVM_INFO @ 1750000: reporter [hdl_top] Time: 1750000

UVM_INFO @ 1800000: reporter [hdl_top] Time: 1800000

UVM_INFO @ 1850000: reporter [hdl_top] Time: 1850000

UVM_INFO @ 1900000: reporter [hdl_top] Time: 1900000

UVM_INFO @ 1950000: reporter [hdl_top] Time: 1950000

UVM_INFO @ 2000000: reporter [hdl_top] Time: 2000000

UVM_INFO @ 2050000: reporter [hdl_top] Time: 2050000

UVM_INFO @ 2100000: reporter [hdl_top] Time: 2100000

UVM_INFO @ 2150000: reporter [hdl_top] Time: 2150000

UVM_INFO @ 2200000: reporter [hdl_top] Time: 2200000

UVM_INFO @ 2250000: reporter [hdl_top] Time: 2250000

UVM_INFO @ 2300000: reporter [hdl_top] Time: 2300000

UVM_INFO @ 2350000: reporter [hdl_top] Time: 2350000

UVM_INFO @ 2400000: reporter [hdl_top] Time: 2400000

UVM_INFO @ 2450000: reporter [hdl_top] Time: 2450000

UVM_INFO @ 2500000: reporter [hdl_top] Time: 2500000

UVM_INFO @ 2550000: reporter [hdl_top] Time: 2550000

UVM_INFO @ 2600000: reporter [hdl_top] Time: 2600000

UVM_INFO @ 2650000: reporter [hdl_top] Time: 2650000

UVM_INFO @ 2700000: reporter [hdl_top] Time: 2700000

UVM_INFO @ 2750000: reporter [hdl_top] Time: 2750000

UVM_INFO @ 2800000: reporter [hdl_top] Time: 2800000

UVM_INFO @ 2850000: reporter [hdl_top] Time: 2850000

UVM_INFO @ 2900000: reporter [hdl_top] Time: 2900000

UVM_INFO @ 2950000: reporter [hdl_top] Time: 2950000

UVM_INFO @ 3000000: reporter [hdl_top] Time: 3000000

UVM_INFO @ 3050000: reporter [hdl_top] Time: 3050000

UVM_INFO @ 3100000: reporter [hdl_top] Time: 3100000

UVM_INFO @ 3150000: reporter [hdl_top] Time: 3150000

UVM_INFO @ 3200000: reporter [hdl_top] Time: 3200000

UVM_INFO @ 3250000: reporter [hdl_top] Time: 3250000

UVM_INFO @ 3300000: reporter [hdl_top] Time: 3300000

UVM_INFO @ 3350000: reporter [hdl_top] Time: 3350000

UVM_INFO @ 3400000: reporter [hdl_top] Time: 3400000

UVM_INFO @ 3450000: reporter [hdl_top] Time: 3450000

UVM_INFO @ 3500000: reporter [hdl_top] Time: 3500000

UVM_INFO @ 3550000: reporter [hdl_top] Time: 3550000

UVM_INFO @ 3600000: reporter [hdl_top] Time: 3600000

UVM_INFO @ 3650000: reporter [hdl_top] Time: 3650000

UVM_INFO @ 3700000: reporter [hdl_top] Time: 3700000

UVM_INFO @ 3750000: reporter [hdl_top] Time: 3750000

UVM_INFO @ 3800000: reporter [hdl_top] Time: 3800000

UVM_INFO @ 3850000: reporter [hdl_top] Time: 3850000

UVM_INFO @ 3900000: reporter [hdl_top] Time: 3900000

UVM_INFO @ 3950000: reporter [hdl_top] Time: 3950000

UVM_INFO @ 4000000: reporter [hdl_top] Time: 4000000

UVM_INFO @ 4050000: reporter [hdl_top] Time: 4050000

UVM_INFO @ 4100000: reporter [hdl_top] Time: 4100000

UVM_INFO @ 4150000: reporter [hdl_top] Time: 4150000

UVM_INFO @ 4200000: reporter [hdl_top] Time: 4200000

UVM_INFO @ 4250000: reporter [hdl_top] Time: 4250000

UVM_INFO @ 4300000: reporter [hdl_top] Time: 4300000

UVM_INFO @ 4350000: reporter [hdl_top] Time: 4350000

UVM_INFO @ 4400000: reporter [hdl_top] Time: 4400000

UVM_INFO @ 4450000: reporter [hdl_top] Time: 4450000

UVM_INFO @ 4500000: reporter [hdl_top] Time: 4500000

UVM_INFO @ 4550000: reporter [hdl_top] Time: 4550000

UVM_INFO @ 4600000: reporter [hdl_top] Time: 4600000

UVM_INFO @ 4650000: reporter [hdl_top] Time: 4650000

from pcie5_phy.

Final Resolution

• we changed the clock period to 2 timeunits instead of 10 timeunits
• Design team removed 12ms timeout in detect state
  @usfmohy

from pcie5_phy.