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aes

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

aes-1

Fully pipelined AES module written in SystemVerilog. WIP.

aes-2

Hardware and software implementation of AES algorithm

aes-encryption

fast AES-128 Encryption only cores

aes_pipe

Pipelined AES

awesome-smartnic

A curated list of awesome smartnic tutorials, papers and projects.

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

dpa-app

Tool to initialize and configure DPAA with classifier policies

fpga-network-stack

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

fpga-sm3-hash

Description of Chinese SM3 Hash algorithm with Verilog HDL

fpga_sm4

FPGA implementation of Chinese SM4 encryption algorithm.

hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

hyperparser

low-cost-and-programmable-crc

Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"

opentitan

OpenTitan: Open source silicon root of trust

panic_osdi20_artifact

perc-p4

Source files of the P4 & Verilog NetFPGA SUME implementation of the s-PERC switch

smx

国家商用加密算法 SMx（SM2,SM3,SM4）

spc

Soft Parser Configuration tool

system-verilog-packet-library

System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers

trex-core

trex-core site