The image-masking-accelerator from matthew-william-lock

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This accelerator uses a Nexys A7 100T FPGA to overlay an one image over another using an image mask and performing masking operations, with the results being displayed over VGA. The purpose of this project was to utilize the parallel nature of FPGAs to create a hardware accelerator for image masking applications.

Pascal 0.01% JavaScript 0.08% Shell 0.27% Batchfile 0.01% HTML 0.09% Tcl 0.07% Verilog 1.42% Coq 7.97% VHDL 89.80% Stata 0.03% Forth 0.01% Makefile 0.01% C++ 0.02% Python 0.01% 1C Enterprise 0.01% SystemVerilog 0.25%

image-masking-accelerator's Introduction

Aspiring Engineer completing an MSc in Embedded Systems Engineering at the KTH Royal Institute of Technology.

Robotics • Machine Learning • Embedded Systems • Web Development • Contact

Embedded Control engineer from South Africa with a passion for robotics. I graduated with a Bachelor of Science in Electrical and Computer Engineering from the University of Cape Town in July 2021 and am completing an MSc in Embedded Systems Engineering at the KTH Royal Institute of Technology in Stockholm, Sweden .

I am passionate about the application of embedded systems and machine learning to robotics and autonomous systems for sustainable development, and currently work as an Embedded Systems Engineer at Ecobloom and an Assistant Researcher at the Swedish Maritime Robotics Centre (SMaRC).