li3tuo4 / rc-fpga-zcu Goto Github PK

Hi @li3tuo4 ,

The default project has 256 MB made available to the Rocket core. I want to increase this to 1 GB. I checked that the address editor for Zynq has 2 GB addressable and I modified the rocketchip_wrapper.v file -

assign S_AXI_araddr = {2'd1, mem_araddr[29:0]};
assign S_AXI_awaddr = {2'd1, mem_awaddr[29:0]};

This should allow it to address memory starting at 1 GB offset and 30 bits means it can address 1 GB of memory. But, with this change, it completely stopped working. Any chisel code/parameters that need to be changed to match?

I am getting the following error while executing make fesvr-zynq.

checking build system type... x86_64-unknown-linux-gnu
checking host system type... Invalid configuration aarch64-linux-gnu': machine aarch64' not recognized
configure: error: /bin/sh scripts/config.sub aarch64-linux-gnu failed

I saw the previous thread as well where they talk about the issue and later said they were able to resolve it but I couldn't figure out any definite solution. Please let me know if I am missing something here.
I am using Vivado, SDK and Petalinxu 2018.3 and I have the Xilinx SDK added to my path as well.

#5 (comment) -- Here replacing config.sub and config.guess seems to solve the issue but replacing from where ?

Hello how are you, I get this error after running ./configure

checking build system type... Invalid configuration aarch64-unknown-linux-gnu': machine aarch64-unknown' not recognized configure: error: /bin/bash ./config.sub aarch64-unknown-linux-gnu failed configure: error: ./configure.gnu failed for lib/libnids-1.21_patched

Regards

Thank you for your detailed tutorial. It helps me a lot to follow your work. Until now, I have finished the long building process. I successfully built the BOOT.bin & image.ub and load them into my SDcard. But when I powered on my board, it just printed two sentences "Xilinx Zynq MP First Stage Boot Loader \n Release 2017.1 Aug 16 2018 - 17:25:43\n" and then blocked. I used the same version Vivado, SDK, Petalinux and BSP, so I'm confused why it happened.
Then, I found a discussion about the same problem on Xilinx forum. I guess the root cause is the version of my board. My version is "ZCU102 Revision 1.1". It may be newer than your board. The older FSBL or pmu.elf may not work on the new board. So I used the pre-built BOOT.bin & image.ub from Xilinx wiki. This time, it started the PS linux system successfully. So I tried rebuilding with the newest BSP and Petalinux, but it reported some errors during petalinux-build process (I have correct the project config file). So I gave up this solution and tried to repackage the BOOT.bin replacing the original fsbl.elf and pmu.elf with the newest version which downloaded from the above link. This time, the u-boot executed successfully but the kernel failed. Now I have no idead about how to fix it?

Greetings and thanks for porting rocket-chip to ZCU102 board!

There is a problem in zcu102/soft_config/config file with a hardcoded path. Do you know how I can generate my own config file to overcome this and also any other issue that may come up?

Thank you for your contribution in making this work public.

I was trying to generate a RV32 variant of RocketChip on ZCU102. I created a new configuration in RocketChip Configs.scala and with changing width-related parameters (manually) from 64 to 32 in testchipip. This generates the bitstream and ARM Linux can boot. I recompiled fesvr-zynq and pk (from your riscv-pk-zcu repo) (not trying bbl at the moment) with SiFive toolchain.
All this flow works but when I try to run the program with ./fesvr_zynq, no output is obtained. It is non hanging the whole system either as Ctrl+C works.

What could I be missing on?

I have followed the instructions to build all the files from scratch (could not use pre-built images due to different board version).
However, when I run ./fesvr-zynq pk hello it just hangs and does not print anything. Same issue with bbl. I need to press Ctrl+C twice to get back. I believe pk and hello are built correctly because spike pk hello on the host works fine. For fesvr-zynq, I have tried both the prebuilt image and my freshly built one with the same result. How do I debug this? I wonder if there's an issue with HTIF or the rocket core itself.

Another question (maybe unrelated): Is a htif uio entry needed in the ARM's device tree? It doesn't look like fesvr-zynq is using /dev/uioX, but rather just /dev/mem.

Greetings Tuo,

I tried building the linux kernel using the configuration file config_freedom according to your tutorial. I tested both the master branch (commit 513ce6d3080b43af80c4f0daaf7436c145c70a23) & linux_u500vc707devkit_config branch (commit db77bd7a8779d776d3f67b8a76ab5973e93604e6), and linux won't boot.

When I try to run ./fesvr-zynq bbl on the zcu102 it hangs there and no output is provided. I tried running the bbl binary in spike and it boots fine, which excludes the possibility of a broken binary file.

On the contrary, the bbl_linux binary included in your repo with the pre-built images boots fine on the FPGA board, so the problem may lie in the kernel configuration file? Did you use the same configuration file for the pre-built images?

Thanks and sorry for bothering you again!
Nick

Hello, when I execute 'make bitstream', I get errors. Please help me. Thank you!

make bitstream
vivado -mode tcl -source src/tcl/make_bitstream_ZynqConfig.tcl

****** Vivado v2019.1 (64-bit)
  **** SW Build 2552052 on Fri May 24 14:47:09 MDT 2019
  **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source src/tcl/make_bitstream_ZynqConfig.tcl
# open_project zcu102_rocketchip_ZynqConfig/zcu102_rocketchip_ZynqConfig.xpr
Scanning sources...
Finished scanning sources
# reset_run synth_1
# reset_run impl_1
# launch_runs synth_1
[Mon Aug  5 14:46:17 2019] Launched synth_1...
Run output will be captured here: /home/dwx/rc-fpga-zcu/zcu102/zcu102_rocketchip_ZynqConfig/zcu102_rocketchip_ZynqConfig.runs/synth_1/runme.log
# wait_on_run synth_1
[Mon Aug  5 14:46:17 2019] Waiting for synth_1 to finish...

*** Running vivado
    with args -log rocketchip_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source rocketchip_wrapper.tcl


****** Vivado v2019.1 (64-bit)
  **** SW Build 2552052 on Fri May 24 14:47:09 MDT 2019
  **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source rocketchip_wrapper.tcl -notrace
Command: synth_design -top rocketchip_wrapper -part xczu9eg-ffvb1156-2-e
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xczu9eg'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xczu9eg'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 4790
---------------------------------------------------------------------------------
Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1562.461 ; gain = 157.719 ; free physical = 61483 ; free virtual = 63848
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'rocketchip_wrapper' [/home/dwx/rc-fpga-zcu/zcu102/src/verilog/rocketchip_wrapper.v:4]
ERROR: [Synth 8-439] module 'system' not found [/home/dwx/rc-fpga-zcu/zcu102/src/verilog/rocketchip_wrapper.v:100]
ERROR: [Synth 8-6156] failed synthesizing module 'rocketchip_wrapper' [/home/dwx/rc-fpga-zcu/zcu102/src/verilog/rocketchip_wrapper.v:4]
---------------------------------------------------------------------------------
Finished Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1691.055 ; gain = 286.312 ; free physical = 61572 ; free virtual = 63937
---------------------------------------------------------------------------------
synthesize failed
INFO: [Common 17-83] Releasing license: Synthesis
3 Infos, 0 Warnings, 0 Critical Warnings and 3 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Vivado Synthesis failed
INFO: [Common 17-206] Exiting Vivado at Mon Aug  5 14:46:32 2019...
[Mon Aug  5 14:46:32 2019] synth_1 finished
wait_on_run: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1396.836 ; gain = 0.000 ; free physical = 61916 ; free virtual = 64281
# launch_runs impl_1 -to_step write_bitstream
ERROR: [Common 17-70] Application Exception: Failed to launch run 'impl_1' due to failures in the following run(s):
synth_1
These failed run(s) need to be reset prior to launching 'impl_1' again.

@li3tuo4

Hi,

I am trying to run synthesis for my design in tcl mode in linux terminal without using GUI in remote desktop provided by my friend.
when I run any command just as an example:
launch_runs synth_1
it shows command not found.

please help me to setup vivado environment

Greetings and thanks for the work! I'm trying to reproduce it on a ZCU102, but having problems getting my compiled BBL to boot (the RISC-V logo is not printed). I've verified that my fesvr and ARM device tree are correct by using the BBL binary from https://github.com/li3tuo4/fpga-images-zcu/tree/893bac7d0a77d3e3cac72f26071daf49e87be61a and everything else from what I generated: it successfully booted to the buildroot prompt and I can log in. But with the BBL I've built the RISC-V core won't boot.

When building BBL according to the tutorial at https://github.com/li3tuo4/rc-zcu102-tutorial I had to change --host=riscv64-unknown-linux-gnu to --host=riscv64-unknown-elf due to riscvarchive/riscv-gcc#140. The resulting BBL, when loaded via a working fesvr (verified by testing against your prebuilt ones), will not print the RISC-V logo. What's wrong?

like CONFIG=SmallBoomConfig
thank you

Hi @li3tuo4 ,

I am trying to get the RISC-V to boot Linux. I followed the steps on the riscv-linux repository and checked out v4.15: https://github.com/riscvarchive/riscv-linux/tree/riscv-linux-4.15 since your prebuilt image was also v4.15. I am able to get Linux to boot, but I'm facing problems with mounting the root dir from the initramfs. I get an error like: Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)

Would you be able to share the following -

1. Your root.cpio file
2. kernel.config
3. busybox.config

Hello,

I am using zcu104 board and I have Vivado v2023.1 (64-bit)

Could you please guide me what to change to use the repo for zcu104?

Thanks,
Edris

Though Vivado2017.1 and SDK2018.2 installed, I got this error when running make bitstream:

Command failed: Part 'xczu9eg-ffvb1156-2-i' not found.

Why Vivado2017.1 does not support this (I have installed Zynq UltraScale+ MPSoC)?

at sbt.ErrorHandling$.wideConvert(ErrorHandling.scala:17)
at sbt.MainLoop$.next(MainLoop.scala:96)
at sbt.MainLoop$.run(MainLoop.scala:89)
at sbt.MainLoop$$anonfun$runWithNewLog$1.apply(MainLoop.scala:68)
at sbt.MainLoop$$anonfun$runWithNewLog$1.apply(MainLoop.scala:63)
at sbt.Using.apply(Using.scala:24)
at sbt.MainLoop$.runWithNewLog(MainLoop.scala:63)
at sbt.MainLoop$.runAndClearLast(MainLoop.scala:46)
at sbt.MainLoop$.runLoggedLoop(MainLoop.scala:30)
at sbt.MainLoop$.runLogged(MainLoop.scala:22)
at sbt.StandardMain$.runManaged(Main.scala:109)
at sbt.xMain.run(Main.scala:38)
at xsbt.boot.Launch$$anonfun$run$1.apply(Launch.scala:109)
at xsbt.boot.Launch$.withContextLoader(Launch.scala:128)
at xsbt.boot.Launch$.run(Launch.scala:109)
at xsbt.boot.Launch$$anonfun$apply$1.apply(Launch.scala:35)
at xsbt.boot.Launch$.launch(Launch.scala:117)
at xsbt.boot.Launch$.apply(Launch.scala:18)
at xsbt.boot.Boot$.runImpl(Boot.scala:41)
at xsbt.boot.Boot$.main(Boot.scala:17)
at xsbt.boot.Boot.main(Boot.scala)

Project loading failed: (r)etry, (q)uit, (l)ast, or (i)gnore? i
[warn] Ignoring load failure: no project loaded.
[error] Expected ID character
[error] Not a valid command: run (similar: plugin, new)
[error] run /home/nicolast0604/rc-fpga-zcu/common/build zynq Top zynq MyFPGAConfig
[error] ^
../common/Makefrag.zcu:91: recipe for target '/home/nicolast0604/rc-fpga-zcu/common/build/Top.MyFPGAConfig.fir' failed
make: *** [/home/nicolast0604/rc-fpga-zcu/common/build/Top.MyFPGAConfig.fir] Error 1