can't boot up the PS on ZCU102 Rev1.1 board about rc-fpga-zcu HOT 55 CLOSED

@bwtang
My board version is HW-Z1-ZCU102 revision 1.1.
I guess even with the same revision number, the boards can be different in the PS due to some unknown reasons.
Anyway, it seems this issue is solved in this post.
It looks like you can just try to use a newer BSP file (this might require you to use a newer petalinux).

So I tried rebuilding with the newest BSP and Petalinux, but it reported some errors during petalinux-build process (I have correct the project config file).

What error did you get?
According to that post and your results (2019.2 version works), this might be the right way.
You basically need to configure the same things that are configured in the config files located in soft_config. And, you need to fix the device tree using .dsti file in the same folder. The things that you need to do with petalinux is in this script.

Good luck.

from rc-fpga-zcu.

Thanks for your reply. Like your advise, I fixed my config file and system-user.dsti (slightly different from the original file) and then rebuild PS kernel with the newest BSP (2019.2) and petalinux (2019.2). But it also reported some errors like that:

[INFO] building project
[INFO] sourcing bitbake
[INFO] generating user layers
[INFO] generating workspace directory
INFO: bitbake petalinux-user-image
Loading cache: 100% |######################################################################################################################| Time: 0:00:02
Loaded 3979 entries from dependency cache.
Parsing recipes: 100% |####################################################################################################################| Time: 0:00:13
Parsing of 2893 .bb files complete (2891 cached, 2 parsed). 3980 targets, 154 skipped, 0 masked, 0 errors.
NOTE: Resolving any missing task queue dependencies
Initialising tasks: 100% |#################################################################################################################| Time: 0:00:07
Checking sstate mirror object availability: 100% |#########################################################################################| Time: 0:16:10
Sstate summary: Wanted 165 Found 16 Missed 298 Current 765 (9% match, 83% complete)
NOTE: Executing SetScene Tasks
NOTE: Executing RunQueue Tasks
ERROR: device-tree-xilinx-v2019.2+gitAUTOINC+a8b39cf536-r0 do_configure: Function failed: do_configure (log file is located at /home/tbw/tmp/test2/build/tmp/work/zcu102_zynqmp-xilinx-linux/device-tree/xilinx-v2019.2+gitAUTOINC+a8b39cf536-r0/temp/log.do_configure.27820)
ERROR: Logfile of failure stored in: /home/tbw/tmp/test2/build/tmp/work/zcu102_zynqmp-xilinx-linux/device-tree/xilinx-v2019.2+gitAUTOINC+a8b39cf536-r0/temp/log.do_configure.27820
Log data follows:
| DEBUG: Executing shell function do_configure
| MISC_ARG is  -hdf_type hdf -yamlconf /home/tbw/tmp/test2/build/tmp/work/zcu102_zynqmp-xilinx-linux/device-tree/xilinx-v2019.2+gitAUTOINC+a8b39cf536-r0/device-tree.yaml
| APP_ARG is  -app "device-tree"
| Using xsct from: /home/tbw/petalinux_2019.2/tools/xsct/bin/xsct
| cmd is: xsct -sdx -nodisp /home/tbw/tmp/test2/build/tmp/work/zcu102_zynqmp-xilinx-linux/device-tree/xilinx-v2019.2+gitAUTOINC+a8b39cf536-r0/dtgen.tcl -ws /home/tbw/tmp/test2/build/../components/plnx_workspace/device-tree -pname device-tree -rp /home/tbw/tmp/test2/build/tmp/work/zcu102_zynqmp-xilinx-linux/device-tree/xilinx-v2019.2+gitAUTOINC+a8b39cf536-r0/git -processor psu_cortexa53_0 -hdf /home/tbw/tmp/test2/build/tmp/deploy/images/zcu102-zynqmp/Xilinx-zcu102-zynqmp.hdf -arch 64  -app "device-tree"  -hdf_type hdf -yamlconf /home/tbw/tmp/test2/build/tmp/work/zcu102_zynqmp-xilinx-linux/device-tree/xilinx-v2019.2+gitAUTOINC+a8b39cf536-r0/device-tree.yaml
| INFO: [Hsi 55-2053] elapsed time for repository (/home/tbw/petalinux_2019.2/tools/xsct/data/embeddedsw) loading 0 seconds
| hsi::open_hw_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 813.422 ; gain = 141.684 ; free physical = 4440 ; free virtual = 28283
| WARNING: quotes to be removed or use 2018.1 version for &sata params param0..param7
| WARNING: quotes to be removed or use 2018.1 version for &sata params param0..param7
| WARNING: quotes to be removed or use 2018.1 version for &sata params param0..param7
| WARNING: quotes to be removed or use 2018.1 version for &sata params param0..param7
| WARNING: quotes to be removed or use 2018.1 version for &sata params param0..param7
| WARNING: quotes to be removed or use 2018.1 version for &sata params param0..param7
| WARNING: quotes to be removed or use 2018.1 version for &sata params param0..param7
| WARNING: quotes to be removed or use 2018.1 version for &sata params param0..param7
| Failed to find amba_pl node !!!
| ERROR: [Hsi 55-1545] Problem running tcl command ::sw_device_tree::generate : Failed to find amba_pl node !!!
|     while executing
| "error "Failed to find $lu_node node !!!""
|     (procedure "get_node_object" line 31)
|     invoked from within
| "get_node_object amba_pl pl.dtsi"
|     invoked from within
| "create_dt_node  -name M_AXI -label M_AXI -unit_addr a0000000 -objects [get_node_object amba_pl pl.dtsi]"
|     ("eval" body line 1)
|     invoked from within
| "eval "create_dt_node ${cmd}""
|     (procedure "add_or_get_dt_node" line 183)
|     invoked from within
| "add_or_get_dt_node -n $drv_handle -l $drv_handle -u $base -d $default_dts -p $bus_node"
|     ("foreach" body line 36)
|     invoked from within
| "foreach drv_handle $ext_axi_intf {
| 			set base [string tolower [get_property BASE_VALUE $drv_handle]]
| 			set high [string tolower [get_property HIGH_V..."
|     (procedure "gen_ext_axi_interface" line 12)
|     invoked from within
| "gen_ext_axi_interface"
|     (procedure "::sw_device_tree::generate" line 21)
|     invoked from within
| "::sw_device_tree::generate device_tree"
| ERROR: [Hsi 55-1442] Error(s) while running TCL procedure generate()
| hsi::generate_target: Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 822.938 ; gain = 9.516 ; free physical = 3019 ; free virtual = 27745
| generate_target failed
|     while executing
| "error "generate_target failed""
|     invoked from within
| "if {[catch {hsi generate_target -dir $project} res]} {
| 	error "generate_target failed"
| }"
|     (file "/home/tbw/tmp/test2/build/tmp/work/zcu102_zynqmp-xilinx-linux/device-tree/xilinx-v2019.2+gitAUTOINC+a8b39cf536-r0/dtgen.tcl" line 38)
| WARNING: /home/tbw/tmp/test2/build/tmp/work/zcu102_zynqmp-xilinx-linux/device-tree/xilinx-v2019.2+gitAUTOINC+a8b39cf536-r0/temp/run.do_configure.27820:1 exit 1 from 'eval xsct -sdx -nodisp /home/tbw/tmp/test2/build/tmp/work/zcu102_zynqmp-xilinx-linux/device-tree/xilinx-v2019.2+gitAUTOINC+a8b39cf536-r0/dtgen.tcl -ws /home/tbw/tmp/test2/build/../components/plnx_workspace/device-tree -pname device-tree -rp /home/tbw/tmp/test2/build/tmp/work/zcu102_zynqmp-xilinx-linux/device-tree/xilinx-v2019.2+gitAUTOINC+a8b39cf536-r0/git -processor psu_cortexa53_0 -hdf /home/tbw/tmp/test2/build/tmp/deploy/images/zcu102-zynqmp/Xilinx-zcu102-zynqmp.hdf -arch 64 ${APP_ARG} ${MISC_ARG}'
| ERROR: Function failed: do_configure (log file is located at /home/tbw/tmp/test2/build/tmp/work/zcu102_zynqmp-xilinx-linux/device-tree/xilinx-v2019.2+gitAUTOINC+a8b39cf536-r0/temp/log.do_configure.27820)
ERROR: Task (/home/tbw/petalinux_2019.2/components/yocto/source/aarch64/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bb:do_configure) failed with exit code '1'
NOTE: Tasks Summary: Attempted 3254 tasks of which 3029 didn't need to be rerun and 1 failed.

Summary: 1 task failed:
  /home/tbw/petalinux_2019.2/components/yocto/source/aarch64/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bb:do_configure
Summary: There was 1 ERROR message shown, returning a non-zero exit code.
ERROR: Failed to build project

According the log, the root cause maybe my system-user.dsti file. Its content is:

/include/ "system-conf.dtsi"
/{
	chosen {
		bootargs = "earlycon clk_ignore_unused root=/dev/mmcblk0p2 rw rootwait rootfstype=ext4 uio_pdrv_genirq.of_id=generic-uio";
		stdout-path = "serial0:115200n8";
	};

        htif_0: htif@a0000000 {
        #address-cells = <1>;
        #size-cells = <1>;
        compatible = "generic-uio", "uio", "uio_pdrv";
        reg = <0x0 0xa0000000 0x0 0x1000>;
        };
gpio-keys {
 sw19 {
 compatible = "gpio-keys";
 label = "sw19";
 status = "disabled";
 };
 };
 leds {
 compatible = "gpio-leds";
 heartbeat_led {
 label = "heartbeat";
 linux,default-trigger = "heartbeat";
 status = "disabled";
};
 };
};

&i2c1 {

	/* FIXME PL i2c via PCA9306 - u45 */
	/* FIXME MSP430 - u41 - not detected */
	i2c-mux@74 { /* u34 */
		i2c@0 { /* i2c mw 74 0 1 */
			/*
			 * IIC_EEPROM 1kB memory which uses 256B blocks
			 * where every block has different address.
			 *    0 - 256B address 0x54
			 * 256B - 512B address 0x55
			 * 512B - 768B address 0x56
			 * 768B - 1024B address 0x57
			 */
			eeprom: eeprom@54 { /* u23 */
				compatible = "atmel,24c08";
				reg = <0x54>;
			};
		};
	};
};

This is my first time to write .dst. I didn't understand its meaning, just copyed from original file and merged it into the default file. I know the riscv-fesvr is related to the dst file. So I want to know its meaning. Do you have some advise?

from rc-fpga-zcu.

@bwtang
This .dtsi file basically adds the device node htif and a few bootargs, to the device tree. Petalinux does not allow users to directly modify the main device tree (dst). This .dtsi file will be used by petalinux during build to merge with the main dst.

Which .hdf file did you use for your petalinux project? The hdf file should be from the vivado project (by export hardware).
In your new .dtsi file, where is the i2c device node from?

from rc-fpga-zcu.

Were you able to successfully boot on rev1.1?

from rc-fpga-zcu.

I have Petalinux 2019 installed on my system, and I am using the 2019 BSP file which is placed in my soft_config folder. when I issue make kernel_image I am receiving the following.

michael@michael-builldmachine:~/git/rc-fpga-zcu/zcu102$ make kernel_image
bash /home/michael/git/rc-fpga-zcu/zcu102/soft_config/petalinux_bd.sh petalinux_proj
INFO: Create project: petalinux_proj
INFO: New project successfully created in /home/michael/git/rc-fpga-zcu/zcu102/petalinux_proj
'/home/michael/git/rc-fpga-zcu/zcu102/soft_config/config' -> '/home/michael/git/rc-fpga-zcu/zcu102/petalinux_proj/project-spec/configs/config'
INFO: Getting hardware description...
INFO: Rename rocketchip_wrapper.hdf to system.hdf
[INFO] generating Kconfig for project
[INFO] silentconfig project
ERROR: Failed to silentconfig project component 
ERROR: Failed to config project.
ERROR: Get hw description Failed!.

Is there something that I need to refactor in order to get BOOT.bin and image.ub to build for rev1.1?

from rc-fpga-zcu.

@FTGStudio Yes, my board is also a rev1.1 and it works perfectly. However, the scripts are made and tested for 2017.1 Vivado and petalinux. Hence, you need to do some necessary changes in the scripts for newer Vivado and petalinux.

ERROR: Get hw description Failed!.

This error seems to say that the hardware definition file .hdf is not correct.
You might need to recreate your .hdf file from vivado project by using export hardware command, after the vivado project is implemented successfully. Make sure the correct .hdf file is put into the place, which is used by petalinux_bd.sh.

Cheers,
Tuo

from rc-fpga-zcu.

I was able to export an updated version of the hardware description file via 2019 vivado. I also built the project with 2019 Petalinux. When I generate my BOOT.bin and image.ub file and load it onto an SD card I see the following serial output from the zcu102 rev1.1 board

Xilinx Zynq MP First Stage Boot Loader
Release 2019.2   Jan 13 2020  -  18:18:43

It seems to be hanging out the FSBL. Any advice from this point on?

from rc-fpga-zcu.

@FTGStudio
According to this post:

On further digging, we stumble upon following thread on Xilinx forum
https://forums.xilinx.com/t5/Embedded-Boot-and-Configuration/Booting-ZCU-102-from-SD-Card/td-p/926649

According to it for ZCU102 rev 1.1, newer boards have a new SODIMM that requires 2018.3 FSBL in order to properly work. 2018.3 FSBL is also back compatible for older boards. Newer ZCU102 board MUST use the 2018.3 FSBL, i.e. 2018.2 or earlier FSBL won't boot.

The official Xilinx answer sheet for this issue is in here.

Cheers

from rc-fpga-zcu.

I'm attempting to build the fesvr-zynq right now, and it cannot seem to link "fesvr". I am following the instructions from the README. Any advice?

/opt/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-linux/bin/../lib/gcc/aarch64-linux-gnu/8.2.0/../../../../aarch64-linux-gnu/bin/ld: cannot find -lfesvr

from rc-fpga-zcu.

Hi @bwtang , have you resolved this problem, I met the same problem as you met.

from rc-fpga-zcu.

I substitute the fsbl.elf and pmufw.elf with the newer one and generate the BOOT.bin and image.ub, but when i boot with sd card, it will halt on starting kernel and cannot enter into the file system.

from rc-fpga-zcu.

Hi @FTGStudio , have you boot the arm linux successfully ?

from rc-fpga-zcu.

@FTGStudio
Did you build riscv-fesvr successfully? Is the $(fesvr-lib) built correctly? This tutorial might be helpful.

from rc-fpga-zcu.

I'm attempting to build the fesvr-zynq right now, and it cannot seem to link "fesvr". I am following the instructions from the README. Any advice?

/opt/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-linux/bin/../lib/gcc/aarch64-linux-gnu/8.2.0/../../../../aarch64-linux-gnu/bin/ld: cannot find -lfesvr

This is because when you compile the fesvr you didn't use aarch64 gcc to compile, you can check your fesvr-zynq Makefile to make sure the gcc host is aarch64 while not x86-64 gcc.

from rc-fpga-zcu.

Hi @FTGStudio , have you boot the arm linux successfully ?

Correct. I was able to build a BOOT.BIN file with the latest zynq_fsbl.elf as well as the pmu.elf and got to linux on the ARM core. @li3tuo4 I was able to build fesvr-lib correctly. The tutorial is what I have been working off of. I am at part 3.2 where I have to build the fesvr and I get the error mentioned above. I see the libfesvr.so, however, I do not see the fesvr executable in the common/build folder.

@botaichang
When I perfrom a make fesvr-zynq there is an initial error while configuring:

/rc-fpga-zcu/rocket-chip/riscv-tools/riscv-fesvr/configure \
--host=aarch64-linux-gnu && \
make libfesvr.so

I have the Xilinx SDK added to my path however I receive an error:

checking build system type... x86_64-unknown-linux-gnu
checking host system type... Invalid configuration `aarch64-linux-gnu': machine `aarch64' not recognized

Any advice?

from rc-fpga-zcu.

I have attempted the following:

./configure --host=aarch64-linux-gnu --build=x86_64-unknown-linux-gnu CC=aarch64-linux-gnu-gcc

I wonder why I keep receving aarch64 not recognized

from rc-fpga-zcu.

After replacing the config.sub and config.guess I was able to run configure with the --host=aarch64-linux-gnu option. When the command make fesvr-zynq compiles I run into the following error:

aarch64-linux-gnu-g++ -O2 -std=c++11 -Wall -L/home/michael/git/rc-fpga-zcu/common/build -lfesvr -Wl,-rpath,/usr/local/lib -I /home/michael/git/rc-fpga-zcu/common/csrc -I /home/michael/git/rc-fpga-zcu/testchipip/csrc -I /home/michael/git/rc-fpga-zcu/rocket-chip/riscv-tools/riscv-fesvr/ -Wl,-rpath,/usr/local/lib  -o /home/michael/git/rc-fpga-zcu/common/build/fesvr-zynq /home/michael/git/rc-fpga-zcu/common/csrc/fesvr_zynq.cc /home/michael/git/rc-fpga-zcu/common/csrc/zynq_driver.cc /home/michael/git/rc-fpga-zcu/testchipip/csrc/blkdev.cc 
/tmp/ccvobrct.o: In function `main':
fesvr_zynq.cc:(.text.startup+0xd4): undefined reference to `tsi_t::tsi_t(int, char**)'
fesvr_zynq.cc:(.text.startup+0x158): undefined reference to `htif_t::done()'
fesvr_zynq.cc:(.text.startup+0x18c): undefined reference to `htif_t::exit_code()'
fesvr_zynq.cc:(.text.startup+0x19c): undefined reference to `tsi_t::~tsi_t()'
fesvr_zynq.cc:(.text.startup+0x200): undefined reference to `tsi_t::tsi_t(int, char**)'
fesvr_zynq.cc:(.text.startup+0x218): undefined reference to `tsi_t::~tsi_t()'
/tmp/ccfPQaab.o: In function `zynq_driver_t::poll()':
zynq_driver.cc:(.text+0x210): undefined reference to `tsi_t::send_word(unsigned int)'
zynq_driver.cc:(.text+0x224): undefined reference to `tsi_t::data_available()'
zynq_driver.cc:(.text+0x240): undefined reference to `tsi_t::switch_to_host()'
zynq_driver.cc:(.text+0x304): undefined reference to `context_t::switch_to()'
zynq_driver.cc:(.text+0x36c): undefined reference to `tsi_t::recv_word()'
/tmp/cchPq4WU.o: In function `BlockDevice::~BlockDevice()':
blkdev.cc:(.text+0x234): undefined reference to `context_t::~context_t()'
/tmp/cchPq4WU.o: In function `BlockDevice::run()':
blkdev.cc:(.text+0x680): undefined reference to `context_t::switch_to()'
/tmp/cchPq4WU.o: In function `BlockDevice::BlockDevice(char const*, unsigned int)':
blkdev.cc:(.text+0xbe0): undefined reference to `context_t::context_t()'
blkdev.cc:(.text+0xc60): undefined reference to `context_t::current()'
blkdev.cc:(.text+0xc78): undefined reference to `context_t::init(void (*)(void*), void*)'
blkdev.cc:(.text+0xd44): undefined reference to `context_t::~context_t()'
collect2: error: ld returned 1 exit status
../common/Makefrag.zcu:215: recipe for target '/home/michael/git/rc-fpga-zcu/common/build/fesvr-zynq' failed

from rc-fpga-zcu.

After replacing the config.sub and config.guess I was able to run configure with the --host=aarch64-linux-gnu option. When the command make fesvr-zynq compiles I run into the following error:

aarch64-linux-gnu-g++ -O2 -std=c++11 -Wall -L/home/michael/git/rc-fpga-zcu/common/build -lfesvr -Wl,-rpath,/usr/local/lib -I /home/michael/git/rc-fpga-zcu/common/csrc -I /home/michael/git/rc-fpga-zcu/testchipip/csrc -I /home/michael/git/rc-fpga-zcu/rocket-chip/riscv-tools/riscv-fesvr/ -Wl,-rpath,/usr/local/lib  -o /home/michael/git/rc-fpga-zcu/common/build/fesvr-zynq /home/michael/git/rc-fpga-zcu/common/csrc/fesvr_zynq.cc /home/michael/git/rc-fpga-zcu/common/csrc/zynq_driver.cc /home/michael/git/rc-fpga-zcu/testchipip/csrc/blkdev.cc 
/tmp/ccvobrct.o: In function `main':
fesvr_zynq.cc:(.text.startup+0xd4): undefined reference to `tsi_t::tsi_t(int, char**)'
fesvr_zynq.cc:(.text.startup+0x158): undefined reference to `htif_t::done()'
fesvr_zynq.cc:(.text.startup+0x18c): undefined reference to `htif_t::exit_code()'
fesvr_zynq.cc:(.text.startup+0x19c): undefined reference to `tsi_t::~tsi_t()'
fesvr_zynq.cc:(.text.startup+0x200): undefined reference to `tsi_t::tsi_t(int, char**)'
fesvr_zynq.cc:(.text.startup+0x218): undefined reference to `tsi_t::~tsi_t()'
/tmp/ccfPQaab.o: In function `zynq_driver_t::poll()':
zynq_driver.cc:(.text+0x210): undefined reference to `tsi_t::send_word(unsigned int)'
zynq_driver.cc:(.text+0x224): undefined reference to `tsi_t::data_available()'
zynq_driver.cc:(.text+0x240): undefined reference to `tsi_t::switch_to_host()'
zynq_driver.cc:(.text+0x304): undefined reference to `context_t::switch_to()'
zynq_driver.cc:(.text+0x36c): undefined reference to `tsi_t::recv_word()'
/tmp/cchPq4WU.o: In function `BlockDevice::~BlockDevice()':
blkdev.cc:(.text+0x234): undefined reference to `context_t::~context_t()'
/tmp/cchPq4WU.o: In function `BlockDevice::run()':
blkdev.cc:(.text+0x680): undefined reference to `context_t::switch_to()'
/tmp/cchPq4WU.o: In function `BlockDevice::BlockDevice(char const*, unsigned int)':
blkdev.cc:(.text+0xbe0): undefined reference to `context_t::context_t()'
blkdev.cc:(.text+0xc60): undefined reference to `context_t::current()'
blkdev.cc:(.text+0xc78): undefined reference to `context_t::init(void (*)(void*), void*)'
blkdev.cc:(.text+0xd44): undefined reference to `context_t::~context_t()'
collect2: error: ld returned 1 exit status
../common/Makefrag.zcu:215: recipe for target '/home/michael/git/rc-fpga-zcu/common/build/fesvr-zynq' failed

A simple way is go to Makefile under riscv-fesvr directory and change CC to xilinx SDK aarch64-linux-gnu-gcc and CXX to xilinx SDK aarch64-linux-gnu-g++ and then make libfesvr.

from rc-fpga-zcu.

Hi @FTGStudio , have you boot the arm linux successfully ?

Correct. I was able to build a BOOT.BIN file with the latest zynq_fsbl.elf as well as the pmu.elf and got to linux on the ARM core. @li3tuo4 I was able to build fesvr-lib correctly. The tutorial is what I have been working off of. I am at part 3.2 where I have to build the fesvr and I get the error mentioned above. I see the libfesvr.so, however, I do not see the fesvr executable in the common/build folder.

@botaichang
When I perfrom a make fesvr-zynq there is an initial error while configuring:

/rc-fpga-zcu/rocket-chip/riscv-tools/riscv-fesvr/configure \
--host=aarch64-linux-gnu && \
make libfesvr.so

I have the Xilinx SDK added to my path however I receive an error:

checking build system type... x86_64-unknown-linux-gnu
checking host system type... Invalid configuration `aarch64-linux-gnu': machine `aarch64' not recognized

Any advice?

Which version of petalinux tool do you use? 2019.2 or 2018.3 ? when i create petalinux project i can only pass the compilation through 2017.1 while other versions make some errors.

from rc-fpga-zcu.

@FTGStudio @li3tuo4
I compile petalinux using petalinux SDK v2017.1, and using 2017.1.bsp file ,then i run the shell soft_config/petalinux_bd.sh to generate BOOT.bin, then i regenerate the BOOT.bin file by replacing the fsbl.elf and pmu.elf, and image.ub file with corresponding files of version 2019.2. Then I can enter kernel starting, but the terminal hangs on "xilinx-zynqmp-dma ffaf0000.dma: ZynqMP DMA driver Probe success", and not enter into linux successfully. Could you give me a help? Thanks

from rc-fpga-zcu.

@botaichang

I was able to upgrade the project by opening up in Vivado and selecting "Report Status". When using the make tools I did have to update entries in the Makefile:

BOARD_MODEL = xilinx.com:zcu102:part0:3.1
PART = xczu9eg-ffvb1156-2-e

Let me know if this helps

from rc-fpga-zcu.

@botaichang
If you have got any issue in ARM Linux boot up, it's highly likely the petalinux flow (ARM Linux build) or vivado project (hardware build) is wrong.
It looks like you tried to use 2019.2 bsp in 2017.1's petalinux project? I guess this is not really robust.

Above all, your fsbl and pmu.elf from 2019.2 files passed through the fsbl stage. This means if you do a proper petalinux 2019.2 project from the starting point, it should work.

@FTGStudio
I think somewhere in the script or makefile, the config.sub is already modifed by sed to
add the aarch64 into the target arch.

That compiler error seems to be that the .o files need to be removed (need a clean rebuild).

from rc-fpga-zcu.

@li3tuo4
yes, you are right. The right way I think shoud be using vivado 2019.2 to generate the *.bit and *.sysdef file, so that next step can use petalinux SDK 2019.02 to generate the BOOT.bin by reading *.bsp of 2019.2. But sadly I have no license of vivado 2019.2 while I can use vivado 2017.1.
So, I use vivado 2017.1 to generate hardware description file *.sysdef and bitstream *.bit. And then try to use petalinux 2019.2 SDK to generate BOOT.bin, but sadly it gives error

ERROR: Failed to silentconfig project component 
ERROR: Failed to config project.
ERROR: Get hw description Failed!.

maybe the petalinux sdk version should be same as vivado version so that it can get the hw description correctly.

So I use petalinux 2017.1 to generate the *fsbl and pmu.elf and then substitute this file with files of 2019.2, but this way is not work. So I don't know what should do next. Can you give some advice?

from rc-fpga-zcu.

I have the design working on rev1.1 now. I can boot up linux on the RISCV core. What version of rocket-chip is this repository using?

from rc-fpga-zcu.

@FTGStudio
You can see it in the git log. The rocket chip is modified based on Commit 7cd3352c3b802c3c50cb864aee828c6106414bb3. Would you like to specify how did you solve the problem? That would be very helpful for people who use newer zcu102 boards.

@botaichang
Based on the Xilinx's official answer, the main difference is made in 2018.3 version.
The older boards can work with the old BSP before 2018.3. The new boards can only work with the new BSPs after and include 2018.3. If you have the license for 2018.3 Xilinx tools, just go with 2018.3.
Regarding the error, did you copy and rename *.sysdef to soft_config/*.hdf? Make sure the path is given correctly (the same question was asked; see previous questions in this issue).

from rc-fpga-zcu.

I am working through each step again to verify, however, at a high level I was able to get it up and running by performing the following actions:

1. Generate bitstream with Vivado 2017.1

2. Open project with Vivado 2019.2, perform the upgrade process by specifying correct board model
   BOARD_MODEL = xilinx.com:zcu102:part0:3.3
   PART = xczu9eg-ffvb1156-2-e

3. Update by selecting "Report -> Report IP Status"

4. Synthesize, and generate new bitstream. Then export .xsa (This is a new format as of 2019.2) and bitstream

5. Use petalinux 2019.2 to start a new project with 2019.2 zcu102 bsp files

6. Configure the project using the .xsa and petalinux-config --get-hw-description=../path/to/xsa
   In the configuration menu disable PL from device tree generation, and ensure that an extended
   partition is selected for rootfs.

7. Generate rootfs configuration petalinux-config -c rootfs (I just used the default settings)

8. Build the project. Once you have BOOT.BIN, and image.ub you can load the existing rootfs that comes included with this project. Execute ./fesvr bbl_linux and a busy box prompt will appear

from rc-fpga-zcu.

thanks @li3tuo4 . I try to build with 2018.3 tools. But when i build with 2018.3 petalinux with running the petalinux_bd.sh , i got these errors. Do you have some ideas about this error. It sames as this error: https://forums.xilinx.com/t5/Embedded-Linux/Petalinux-2018-1-build-errors-missing-rootfs-files/m-p/1029604#M37135, but it seems haven't resolved.

/build/tmp/work/plnx_zynqmp-xilinx-linux/packagegroup-core-boot/1.0-r17/recipe-sysroot-native/usr/lib/rpm/rpmrc: No such file or directory
/build/tmp/work/plnx_zynqmp-xilinx-linux/packagegroup-core-boot/1.0-r17/recipe-sysroot-native/usr/lib/rpm/platform/ppc64le-linux/macros: No such file or directory
/build/tmp/work/plnx_zynqmp-xilinx-linux/packagegroup-core-boot/1.0-r17/recipe-sysroot-native/usr/lib/rpm/platform/armv3l-linux/macros: No such file or directory
/build/tmp/work/plnx_zynqmp-xilinx-linux/packagegroup-core-boot/1.0-r17/recipe-sysroot-native/usr/lib/rpm/platform/geode-linux/macros: No such file or directory
/build/tmp/work/plnx_zynqmp-xilinx-linux/packagegroup-core-boot/1.0-r17/recipe-sysroot-native/usr/lib/rpm/platform/mips64r6-linux/macros: No such file or directory
......

from rc-fpga-zcu.

thanks @li3tuo4 . I try to build with 2018.3 tools. But when i build with 2018.3 petalinux with running the petalinux_bd.sh , i got these errors. Do you have some ideas about this error. It sames as this error: https://forums.xilinx.com/t5/Embedded-Linux/Petalinux-2018-1-build-errors-missing-rootfs-files/m-p/1029604#M37135, but it seems haven't resolved.

/build/tmp/work/plnx_zynqmp-xilinx-linux/packagegroup-core-boot/1.0-r17/recipe-sysroot-native/usr/lib/rpm/rpmrc: No such file or directory
/build/tmp/work/plnx_zynqmp-xilinx-linux/packagegroup-core-boot/1.0-r17/recipe-sysroot-native/usr/lib/rpm/platform/ppc64le-linux/macros: No such file or directory
/build/tmp/work/plnx_zynqmp-xilinx-linux/packagegroup-core-boot/1.0-r17/recipe-sysroot-native/usr/lib/rpm/platform/armv3l-linux/macros: No such file or directory
/build/tmp/work/plnx_zynqmp-xilinx-linux/packagegroup-core-boot/1.0-r17/recipe-sysroot-native/usr/lib/rpm/platform/geode-linux/macros: No such file or directory
/build/tmp/work/plnx_zynqmp-xilinx-linux/packagegroup-core-boot/1.0-r17/recipe-sysroot-native/usr/lib/rpm/platform/mips64r6-linux/macros: No such file or directory
......

I made some changes for soft_config/config file , change some version from 2017.1 to 2018.3, and after compile, now gives this error: there is no fsbl directory so it cannot compile by make.

zcu102/petalinux_proj_201803/build/tmp/work/plnx_zynqmp-xilinx-linux/fsbl/2018.3+gitAUTOINC+56f3da2afb-r0/build/fsbl: No such file or directory

from rc-fpga-zcu.

Hi @li3tuo4 , after I made patch for fsbl with 2018.3, I can now start the u-boot but I still cannot mount root-fs successfully. The error information as follows:

 Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(179,2)

could you give me a help for this problem? Thanks very much.

from rc-fpga-zcu.

@botaichang
It seems your root file system is created incorrectly. Carefully check the rootfs config flow in petalinux where the initramfs is created. Also, verify the way you put the initramfs into the SD card is correct.

from rc-fpga-zcu.

Hi @li3tuo4, thanks for your help, I can boot arm linux after make some patch according to
https://forums.xilinx.com/t5/Embedded-Linux/Looking-for-info-on-how-Petalinux-2018-3-manages-the-FSBL-ZCU102/td-p/951758.

Now I have some questions here:

1. After I launch riscv linux, If I want to generate some files in riscv linux, how can I export these files out to arm linux filesystem.

2. When I enter into the riscv linux system, the memory size is only 90M Byte.And if i want to enlarge the memory size of riscv linux filesystem ,how should i do?

from rc-fpga-zcu.

@botaichang
At present, you cannot transfer the files out from the riscv-linux, unless you use pk instead. You can copy the content via console. Some users are trying to create an ethernet facility for this rocket chip.

The current config of physical memory is 256 MB by default for rocket chip. Your riscv-linux probably is not configured to make use of all the memory available? You can first check the riscv-linux config. If you do require physical memory larger than 256 MB, you need to modify the FPGA config in vivado and riscv-linux config.

from rc-fpga-zcu.

Thank you @FTGStudio for the detailed steps. I am trying to replicate the same steps on my board (Rev 1.1 with Micron MTA4ATF51264HZ-2G6E1).
I can boot ARM Linux successfully with this, but after launching the frontend server, the system just hangs and does not respond to even Ctrl+C. This is the case with both given initramfs and all the components compiled individually with riscv64-linux-gnu-gcc and ARM GCC (part of Vitis 2019.2).

I think maybe there might be some additional steps required in the device tree and/or petalinux configuration apart from what you have mentioned above.
I tried to copy the HTIF part of the device tree from the given repository to the one generated by petalinux as per your steps (https://pastebin.com/RpHippWe)
This does not seem to have any effect either.

This is my petalinux config - https://pastebin.com/WBTTtbPW

I would be really thankful if you could guide me on what steps might be missing in our attempt.

from rc-fpga-zcu.

Hello,
I also got Error when I tried to build the fesvr-zynq. Could you give some tips how to solve this issues?:

aarch64-linux-gnu-g++ -O2 -std=c++11 -Wall -L/home/thaising/rc-fpga-zcu32/common/build -lfesvr -Wl,-rpath,/usr/local/lib -I /home/thaising/rc-fpga-zcu32/common/csrc -I /home/thaising/rc-fpga-zcu32/testchipip/csrc -I /home/thaising/rc-fpga-zcu32/rocket-chip/riscv-tools/riscv-fesvr/ -Wl,-rpath,/usr/local/lib -o /home/thaising/rc-fpga-zcu32/common/build/fesvr-zynq /home/thaising/rc-fpga-zcu32/common/csrc/fesvr_zynq.cc /home/thaising/rc-fpga-zcu32/common/csrc/zynq_driver.cc /home/thaising/rc-fpga-zcu32/testchipip/csrc/blkdev.cc
/tmp/ccciMtvm.o: In function main': fesvr_zynq.cc:(.text.startup+0xc0): undefined reference to tsi_t::tsi_t(int, char**)'
fesvr_zynq.cc:(.text.startup+0x140): undefined reference to htif_t::done()' fesvr_zynq.cc:(.text.startup+0x174): undefined reference to htif_t::exit_code()'
fesvr_zynq.cc:(.text.startup+0x180): undefined reference to tsi_t::~tsi_t()' fesvr_zynq.cc:(.text.startup+0x1e8): undefined reference to tsi_t::tsi_t(int, char**)'
fesvr_zynq.cc:(.text.startup+0x204): undefined reference to tsi_t::~tsi_t()' /tmp/ccVXNCKe.o: In function zynq_driver_t::poll()':
zynq_driver.cc:(.text+0x204): undefined reference to tsi_t::send_word(unsigned int)' zynq_driver.cc:(.text+0x218): undefined reference to tsi_t::data_available()'
zynq_driver.cc:(.text+0x238): undefined reference to tsi_t::recv_word()' zynq_driver.cc:(.text+0x24c): undefined reference to tsi_t::data_available()'
zynq_driver.cc:(.text+0x25c): undefined reference to tsi_t::switch_to_host()' zynq_driver.cc:(.text+0x368): undefined reference to context_t::switch_to()'
/tmp/ccl7Rm27.o: In function BlockDevice::~BlockDevice()': blkdev.cc:(.text+0x1c4): undefined reference to context_t::~context_t()'
/tmp/ccl7Rm27.o: In function BlockDevice::run()': blkdev.cc:(.text+0x6a8): undefined reference to context_t::switch_to()'
/tmp/ccl7Rm27.o: In function BlockDevice::BlockDevice(char const*, unsigned int)': blkdev.cc:(.text+0xa10): undefined reference to context_t::context_t()'
blkdev.cc:(.text+0xa8c): undefined reference to context_t::current()' blkdev.cc:(.text+0xaa4): undefined reference to context_t::init(void ()(void), void*)'
blkdev.cc:(.text+0xc24): undefined reference to `context_t::~context_t()'
collect2: error: ld returned 1 exit status
../common/Makefrag.zcu:214: recipe for target '/home/thaising/rc-fpga-zcu32/common/build/fesvr-zynq' failed
make: *** [/home/thaising/rc-fpga-zcu32/common/build/fesvr-zynq] Error 1

from rc-fpga-zcu.

@Thaising-Taing It seems that you did not build and install riscv-fesvr in riscv-tools properly.

from rc-fpga-zcu.

@Thaising-Taing It seems that you did not build and install riscv-fesvr in riscv-tools properly.

I re-installed riscv-fesvr many times and still facing the same issues when I tried to "make fesvr-zynq". I thought because of this Frontend Issues; likewise, I cannot call the RISCV when I booted them successfully on FPGA. When I typed "LD_LIBRARY_PATH=./ ./fesvr-zynq bbl" as your document told, it is stucking without showing any result, but I am sure that my Spike, pk, bbl are built successfully. The fesvr-zynq that you saw in this picture, I copied from some website that they used to build them and I import directly to my linux. Could you help give some suggestion for both issues that I am facing right now?

from rc-fpga-zcu.

If you have not got fesvr-zynq built right due to this linking error, your fesvr-zynq execution on FPGA would not work.

With regard to your error, try to remove content in "common/build" and rebuild from riscv-fesvr.

Does executing this fesvr-zynq without arguments show anything (should show help content) on FPGA? If it shows, the error is in pk.

from rc-fpga-zcu.

If you have not got fesvr-zynq built right due to this linking error, your fesvr-zynq execution on FPGA would not work.

With regard to your error, try to remove content in "common/build" and rebuild from riscv-fesvr.

Does executing this fesvr-zynq without arguments show anything (should show help content) on FPGA? If it shows, the error is in pk.

1. I already followed your step and tried to rebuild the riscv-fesvr and then I removed all the common/build and use "make fesvr-zynq" in the /rc-fpga-zcu/zcu102 directory to rebuild the fesvr-zynq again. it is still Error. This fesvr-zynq is a very difficult part for me even i copied this fesvr-zynq from another, it is still not calling the RISCV Core to wake up. This time it cannot find the "-lfesvr library". Could you help further check and provide more solution for this fesvr-zynq? The Figure shown as below
2. You asked me about the fesvr-zynq that I copied from internet. When I used this fesvr-zynq, it is stucking. It doesn't show any error message. Thank You.
   

from rc-fpga-zcu.

The error seems to tell that libfesvr.so is not not compatible. I guess you compiled that .so file for a wrong target architecture. It should target aarch64.

You can try again with the FPGA after you have got the right fesvr-zynq.

from rc-fpga-zcu.

The error seems to tell that libfesvr.so is not not compatible. I guess you compiled that .so file for a wrong target architecture. It should target aarch64.

You can try again with the FPGA after you have got the right fesvr-zynq.

Where should I check to make them target to the aarch64? I already added the aarch64 machine to the config.sub file inside the riscv-fesvr directory. Could you help provide me more information to fix this frontend server? I got stuck in here for nearly 3months.

from rc-fpga-zcu.

You can check using file or readelf command on the .so file.

from rc-fpga-zcu.

You can check using file or readelf command on the .so file.

This the result that I used the “file libfesvr.so” as what you recommended. And another figure is what I added aarch64 to config.sub file in the riscv-fesvr folder. Could you help check and what is wrong with this that you said it is not target aarch64?

from rc-fpga-zcu.

Your snapshot shows it's targeting x86, not aarch64. Try to rebuild libfesvr and read the log.

from rc-fpga-zcu.

Your snapshot shows it's targeting x86, not aarch64. Try to rebuild libfesvr and read the log.

In your Project, where should I change to make them target the aarch64? I didn't see the instructions that help guide to map them to target aarch64 expect the config.sub inside the riscv-fesvr folder.

from rc-fpga-zcu.

If everything goes right, it should be aarch64 directly. Something is not correct in build process.

from rc-fpga-zcu.

If everything goes right, it should be aarch64 directly. Something is not correct in build process.

I already made them target to aarch64 now, but the error message is getting to my First Comment again. The GCC cannot compile the code to build fesvr-zynq. It is so strange. Could you help refer to the images below and gave more specific solution to fix this issues? I fixed and built everything again for riscv-tools.

from rc-fpga-zcu.

Do you have the full error log? It's either libfesvr.so in common/build not recognized by compiler or libfesvr.so not having those objects.

from rc-fpga-zcu.

Do you have the full error log? It's either libfesvr.so in common/build not recognized by compiler or libfesvr.so not having those objects.

This is my log file that I obtained from the build "make fesvr-zynq" and another is the full error message. Could you help check again the screenshot and config.log file that I attached and give me more direction to overcome this issues?

config.log

from rc-fpga-zcu.

These missing references are defined in riscv-fesvr (for example tsi_t), which should be in libfesvr.so. Can you see if these symbols are in your libfesvr.so by readelf or objdump?

from rc-fpga-zcu.

These missing references are defined in riscv-fesvr (for example tsi_t), which should be in libfesvr.so. Can you see if these symbols are in your libfesvr.so by readelf or objdump?

This is what i obtained from the objdump file. There has alot of things. How could I check them one by one? if it possible can I obtained the file that already built for the riscv-tools or riscv-fesvr from you directly? I spent too long time with Project and now my Professor wished to stop me from this Project if I still have no result to demo. Could you help give more details on this fesvr-zynq?

config.log
build.log

from rc-fpga-zcu.

Sorry to hear that your project is not progressing for so long. Usually riscv-fesvr is not problematic. I don't have a proper local copy of this repository right now, but I found an old archive and uploaded the binaries to this repository. Now you can directly download these two binaries. Use LD_LIBRARY_PATH=./ when you execute fesvr-zynq on FPGA. If your FPGA board is zcu102, things should be smooth. Good luck!

from rc-fpga-zcu.

Sorry to hear that your project is not progressing for so long. Usually riscv-fesvr is not problematic. I don't have a proper local copy of this repository right now, but I found an old archive and uploaded the binaries to this repository. Now you can directly download these two binaries. Use LD_LIBRARY_PATH=./ when you execute fesvr-zynq on FPGA. If your FPGA board is zcu102, things should be smooth. Good luck!

I tried again with your Fesvr-Zynq. It is still stucking without calling the RISCV Core to wake up. It is so strange. My Board is ZCU102. Could you give me the idea why is it stucking?

from rc-fpga-zcu.

If fesvr-zynq alone does not show anything, this could be your ARM hardware side is not right. It could be new htif device, which is in charge of communicating between ARM and RISC-V worlds, is not correctly implemented. Did you encounter any error during the hardware generation? And for ARM OS, Petalinux must include the device node for htif in device tree? If time is stringent for you to debug this, you probably should consider different options. What is your project about? Do you have other options?

from rc-fpga-zcu.

If fesvr-zynq alone does not show anything, this could be your ARM hardware side is not right. It could be new htif device, which is in charge of communicating between ARM and RISC-V worlds, is not correctly implemented. Did you encounter any error during the hardware generation? And for ARM OS, Petalinux must include the device node for htif in device tree? If time is stringent for you to debug this, you probably should consider different options. What is your project about? Do you have other options?

When I build the riscv-tools, I found their has no error, but we have a few warnings. After that, I run make bitstream and create the vivado project. There has no issues and it can working properly when I generated bitstream and program to FPGA. My Project is related to RISCV Soft IP Core, and I saw your Project is gorgeous as it provided the step to call the RISCV Core which run on software stack of ARM. it is so interesting and it is my first time that I run hardware communicate with software, but we encountered so many bugs on your Project. If it is possible, could you help update the whole Project and Guideline. I have a question, the ROCKET CHIP is running in the PL Side of FPGA, right? I saw in your project has two part SYSTEM (maybe ARM Processor PS Part) and another TOP (maybe Rocket Chip). Furthermore, I do not have another Options yet.

from rc-fpga-zcu.

This repository was used by quite a few people at my old research group and we found it generally works fine. Most people encounter problem due to different Vivado versions or board versions, and these problems are out of the current scope of this project. I am fully employed for other projects at the moment, hence I cannot spend much time in enriching this repo. I feel there is something subtle in your dev environment, which causes this problem. Can you find any experienced ZYNQ-FPGA person to take a look at your problem directly at your dev machine?

To answer your questions. Yes, rocket chip is implemented in LUTs etc on PL side and ARM things are hard IPs on PS side. There is a top module instantiates and connects ARM system and PL design, and in this case, PL design is rocket chip. If ZYNQ development is not comfortable to you, you can consider using pure PL FPGA implementations of rocket chip, such as lowrisc, or, chipyard, which includes an on-cloud FPGA-based simulation solution called firesim. If you have further questions or improvement ideas on this repo, I am happy to provide suggestions. Cheers.

from rc-fpga-zcu.