A community-driven compilation of RISC-V resources and learning material. The list is dynamically updated by the community and categorized based on different contexts of the RISC-V scope, taking also into account different levels of experience/knowledge, allowing anyone interested in RISC-V to discover RISC-V resources and relevant content (courses, software, documentation, articles etc.) in an organized fashion. Feel free to navigate through the resources listed below with their descriptions.
RISC-V is an open standard Instruction Set Architecture (ISA) based on established Reduced Instruction Set Computer (RISC) principles.
👋 Want to learn about RISC-V? Check out the Beginner-Level or Intermediate-Level learning resources.
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For those with little or no knowledge of digital logic design. After studying the Digital Design book in this section, you could jump to the intermediate-level edx RVfpga course if you wish as it expands on concepts discussed in the book.
| Resource | Author(s) | Description | Access | Date added |
|---|---|---|---|---|
| Digital Design and Computer Architecture RISC-V edition (good starting point) | Sarah L. Harris, David M. Harris | Covers the foundational knowledge of digital logic design and segues smoothly into RISC-V Processor implementation. Topics covered here include : Number systems and digital representation, Semiconductors and transistors, Logic Gates and Digital Design, C Programming, RISC-V Architecture, RISC-V Assembly, Memory systems, Embedded I/O systems | [Amazon book link] | |
| Nand2Tetris (optional) | Noam Nisan, Shimon Schocken | A free hands-on tutorial on building a general-purpose computer from logic gates using a hardware simulator. Taking this course is optional. | [webpage] | |
| learn-FPGA episode I: from blinky to RISC-V | BrunoLevy | A beginner's introduction to digital design of a RISC-V softcore on FPGAs. Episode I gently starts from a very basic blinker in VERILOG and morphs it step by step into a basic yet fully functional RISC-V SOC. It is also explained how to write programs in C and assembly for the SOC. (Required background: Basic knowledge of VERILOG) |
[GitHub] |
A collection of more advanced learning resources for RISC-V
| Resource | Author(s) | Description | Access | Date added |
|---|---|---|---|---|
| Computer Organization and Design RISC-V edition: The Hardware Software Interface (2nd edition) (good starting point) | David A. Patterson, John L. Hennesy | Covers the RISC-V Instruction Set in general and does an in-depth examination of the core RISC-V instructions. It also does a deep dive into RISC-V processor implementations. Each chapter includes real-world applications by tying concepts discussed with available modern computers. The book also highlights the interactions between hardware and software by continuously optimizing a sample software program based on the new hardware concepts introduced in each chapter. (Required background: knowledge of Logic design is needed to follow the contents of this book) |
[Amazon book link] | |
| Computer Architecture with an Industrial RISC-V Core [RVfpga] | Sarah Harris, Daniel Chaver-Martinez | This free EdX course expands on topics covered in Digital Design and Computer Architecture, RISC-V edition with hands-on learning. This course shows how to target a commercial RISC-V Core and RISC-V system-on-chip (SoC) to FPGA, program the RISC-V SoC, and add more functionalities to the RISC-V SoC | [Edx course link] | |
| learn-FPGA episode II: pipelining | BrunoLevy | This tutorial explains how to transform the basic softcore from episode I into an efficient pipelined processor. The tutorial follows a step-by-step approach, starting from a 5-states processor, transforming the states into stages, and solving data and control hazards by first observing what happens in real programs thanks to the included debugger/disassembler. Then it is explained how to gain more performance using register forwarding. Finally, branch prediction is introduced, from the simplest static branch prediction to more elaborate ones (gshare). The effect of the different optimizations are demonstrated using different codes (the classical dhrystones and coremark benchmarks, and a program that computes an image using raytracing). (Required background: It is highly recommended to read episode I before episode II !) |
[GitHub] | |
| Computer Architecture: A Quantitative Approach(6th edition) | David A. Patterson, John L. Hennesy | Covers advanced computer architecture concepts pertaining to high performance computing principles and domain specific architectures along with examples and exercises pertaining to the RISC-V ISA-(6th Edition onwards). This is a step-up from the first book,(Hardware-Software Interface), with advanced concepts like Instruction , Data and Thread Level Parallelism along with introduction to Vector, SIMD and GPU architectures.It also continues the tradition of using real-world examples to demonstrate the concepts, by introducing memory organizations and architectures of ARM Cortex A8, Intel Core i7, Nvidia GTX-280 GPUs and so on. (Required Background: It is recommended that you first read the Hardware Software Interface before this book !) |
[Amazon book link] | |
| Tutorial: RISC-V Vector Extension Demystified | Thang Tran | A very in-depth, three hour long video introduction to the RISC-V Vector extension. | [Youtube video] | |
| Learn with SHAKTI | [Shakti - RISE Lab, IITM] | A tutorial on RISC-V assembly programming using the RISC-V toolchain (Spike, riscv-pk, OpenOCD) and basic examples and assignments. More elaborate RISC-V ASM examples can be found in the: [Shakti RISC-V ASM Programmer Manual Part I]. | [Link to: Learn with Shakti] | 21-12-2023 |
A collection of tools that can be used along with the beginner or intermediate-level learning resources for a better understanding or visualization of the RISC-V ISA
| Resource | Description | Access | Date added |
|---|---|---|---|
| emulsiV | emulsiV is a visual simulator for a simple RISC processor called Virgule. Virgule is a 32-bit RISC processor core that implements a minimal subset of the RISC-V instruction set. Here, “minimal” means that Virgule accepts only the instructions that a C compiler would generate from a pure stand-alone C program. | [website] | 20-12-2023 |
| RISC-V Instruction Encoder/Decoder | This tool is an online encoder/decoder for RISC-V instructions. Users can input RISC-V instructions in their assembly or binary format and get the full conversion from one to the other. | [website] | 20-12-2023 |
| CREATOR | CREATOR is a didactic simulator that allows the development, simulation, and debugging of RISC-V (RV32IMFD) assembly programs intuitively and interactively. It is a web application, so it can be used on any type of device (desktop, tablet, smartphone, etc.) without installing additional software. Only a modern web browser (Google Chrome, Mozilla Firefox, Apple Safari, etc.) is required. | [website] | 20-12-2023 |
| QtRvSim - RISC-V CPU Simulator with Cache and Pipeline Visualization | QtRvSim is educational simulator with pipeline and cache visualization (RV32IMA/RV64IMA). It supports even M-mode ecalls, ACLINT MTIMER, MSWI, SSWI, related CSR registers, serial port Rx and Tx interrupts and more. | [Github] | 20-12-2023 |
| RVV intrinsics viewer | A third party documentation website for the vector extension intrinsics, currently including pretty much all intrinsics variations, and fuzzy search. This can be a useful resource when writing rvv code. | [website] | 20-12-2023 |
A list of all open RISC-V Implementations
| Name | Description | Access | Date added |
|---|---|---|---|
| Pequeno | Pequeno aka pqr5 is a pipelined in-order RISC-V CPU Core compliant with RV32I | [Github] | 20-12-2023 |
| Resource | Description | Access |
|---|---|---|
| Member Benefits and Welcome deck | A set of slides useful for new RISC-V members to familiarize themselves with the scope/organization of the RISC-V community and learn about membership benefits, as well as how to integrate into the community as a member. | [Google Doc] |
| Getting Started Guide for RISC-V Members | This document is intended to give a member’s overview of the RISC-V technical organizations. The intended audience is both for new members as well as a reference for existing members. | [Google Doc] |
| RISC-V Technical Wiki | This page serves as the main anchor point for the most important pieces of technical information for RISC-V. If you're looking for something technical, start here. | [webpage] |
| RISC-V Lifecycle Guide | This document has been created to facilitate RISC-V member participation in the key activities involved in creating and running groups, writing of specifications, and contributing open-source software in support of RISC-V architectures. It is a guide, not the rules. | [Google Doc] |
| RISC-V Repository Map | A central point that directs to different repositories relevant to the RISC-V ecosystem. It includes the technical and non-technical, ISA and non-ISA related, software related, as well as collaboration related repositories for RISC-V available on Github. | [webpage] |
| Resource | Author(s) | Description | Access |
|---|---|---|---|
| Design of the RISC-V Instruction Set Architecture | Andrew Waterman | Andrew Waterman’s Doctorate of Philosophy dissertation in the University of California, Berkeley, about the RISC-V ISA. It covers how RISC-V is a well structured small base ISA with a variety of optional extensions, making RISC-V convenient for a range of purposes from research and education, low-power embedded devices, to more general-purpose, high-performance computing, with the existence of these optional extensions. It provides a comparison of RISC-V to other popular ISAs as well. | [pdf] |
| Past, Present and Future of RISC-V | Krste Asanović | [YouTube video] | |
| Is RISC-V the Future | Roddy Urquhart | [webpage] |
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