kcelebi / riscv-assembler Goto Github PK

addi s0 x0 10
addi s1 x0 10

loop:
	addi s1 x0 -1 ; I know it's the same as s1 = -1
	beq s1 x0 out
	beq x0 x0 loop

out:
	addi s1 s0 -32

00000000101000000000010000010011
00000000101000000000010010010011
11111111111100000000010010010011
00000000000001001000010001100011
01111100000000000000101011100011
11111110000001000000010010010011

0 111110 00000 00000 000 1010 1 1100011
^ ^^^^^^ ^^^^^ ^^^^^     ^^^^ ^
| |      |     rs1       |    |
| |      rs2             |    imm[11]
| imm[10:5]              imm[4:1]
imm[12]

0000 1 111110 1010 0 = 4052

v--- different leading bit
1 111111 00000 00000 000 1100 1 1100011 <- RARS
0 111110 00000 00000 000 1010 1 1100011 <- this assembler

C:\Users\user0\riscv-assembler\tests\assembly>python
Python 3.7.3 (v3.7.3:ef4ec6ed12, Mar 25 2019, 21:26:53) [MSC v.1916 32 bit (Intel)] on win32
Type "help", "copyright", "credits" or "license" for more information.
>>> from riscv_assembler.convert import AssemblyConverter
>>> cnv = AssemblyConverter()
>>> cnv.convert("test0.s")
-----Writing to binary file-----
Output file: test0.bin
Number of instructions: 1
>>> #outputs to binary file simple.bin
...
>>> from riscv_assembler.convert import AssemblyConverter
>>> cnv = AssemblyConverter()
>>> cnv.convert("test0.s")
-----Writing to binary file-----
Output file: test0.bin
Traceback (most recent call last):
  File "<stdin>", line 1, in <module>
  File "C:\Users\user0\AppData\Local\Programs\Python\Python37-32\lib\site-packages\riscv_assembler\convert.py", line 589, in convert
    return self.__post()
  File "C:\Users\user0\AppData\Local\Programs\Python\Python37-32\lib\site-packages\riscv_assembler\convert.py", line 533, in __post
    os.mkdir(f"{fname[:-2]}/bin")
FileExistsError: [WinError 183] File/Folder existed, could not create the file or folder: 'test0/bin'
>>> #outputs to binary file simple.bin

   lw s2, 8(sp) #works
   lb s2, 8(sp) #throws error
   lh s2, 8(sp) #throws error

elif clean[0] == "lw":  #<--lb and lh should be added
	res.append(self.I_type(clean[0], self.__reg_map(clean[3]), clean[2], self.__reg_map(clean[1])))

elif clean[0] == "lw" or clean[0] == "lb" or clean[0] == "lh":
	res.append(self.I_type(clean[0], self.__reg_map(clean[3]), clean[2], self.__reg_map(clean[1])))

IndexError                                Traceback (most recent call last)
<ipython-input-2-5a83df4fad26> in <module>
      1 from riscv_assembler.convert import AssemblyConverter
      2 cnv = AssemblyConverter(output_type="bp")
----> 3 cnv.convert("test.s")

~/<dir>/python3.9/site-packages/riscv_assembler/convert.py in convert(self, filename)
    578                 self.filename = filename
    579                 self.code = self.__read_in_advance()
--> 580                 self.instructions = self.__get_instructions()
    581 
    582                 if self.hexMode:

~/<dir>/python3.9/site-packages/riscv_assembler/convert.py in __get_instructions(self)
    413                         line = self.code[i]
    414 
--> 415                         response = self.__interpret(line,i)
    416                         if -1 not in response:
    417                                 instructions.extend(response)

~/<dir>/python3.9/site-packages/riscv_assembler/convert.py in __interpret(self, line, i)
    458                         #print(res)
    459                 elif clean[0] in self.S_instr:
--> 460                         res.append(self.S_type(clean[0], self.__reg_map(clean[3]), self.__reg_map(clean[1]), clean[2]))
    461                         #print(res)
    462                 elif clean[0] in self.SB_instr:

IndexError: list index out of range

addi x2, x0, 1

loop:
   sub x1, x1, x2
   sw  x1, 4(x0) 
   blt x0, x1, loop

0x00100113
0x402080b3
0x00102223
0x7c104ae3

00100113
402080b3
00102223
fe104ce3