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ROHD Hardware Component Libary

A hardware component library developed with ROHD. This library aims to collect a set of reusable, configurable components that can be leveraged in other designs. These components are also intended as good examples of ROHD hardware implementations.

Check out the generator web app, which lets you explore some of the available components, configure them, and generate SystemVerilog.

This project is always improving and growing! In a given category, initial components are primarily focused on correctness with room for optimization from there. Please feel free to contribute or provide feedback. Check out CONTRIBUTING for details on how to contribute.

This project is not intended to be the only place for reusable hardware components developed in ROHD. It's not even intended to be the only library. Contributions are welcomed to this library, but developers are also welcome to build independent packages or libraries, even if they may overlap.

Guidelines for Components

  • All hardware components should be Modules so that they are convertible to SystemVerilog
  • Components should be general and easily reusable
  • Components should be as configurable as may be useful
  • Components must be extensively tested
  • Components must have excellent documentation and examples
  • The first component in a category should be the simplest
  • Focus on breadth of component types before depth in one type
  • Add extensions to other classes to make component usage easier, when appropriate

Component List

See the component list for documentation on components and plans for future component development.

Some examples of component categories include:

  • Encoders & Decoders
  • Arbiters
  • FIFOs & Queues
  • Find
  • Count
  • Sort
  • Arithmetic
  • Rotate
  • Counters
  • Pseudorandom
  • Error checking & correction
  • Data flow
  • Memory
  • Standard interfaces
  • Models

Copyright (C) 2023 Intel Corporation
SPDX-License-Identifier: BSD-3-Clause

rohd-hcl's People

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rohd-hcl's Issues

Prefix trees

Motivation

Useful for efficient encoders and arithmetic

Desired solution

Implement generic capabilities for generating prefix trees

Alternatives considered

No response

Additional details

No response

Build version-specific constructors for `ApbInterface`

Motivation

The APB spec includes a table describing which signals are optional or not based on APB version. It would be helpful for users to have a mechanism to properly instantiate a version of the APB interface that follows the spec rules for that version.

Desired solution

Maybe special named constructors which only expose proper configurability based on the version of the APB interface being constructed.

Alternatives considered

No response

Additional details

No response

Round-robin arbiter

Motivation

A round-robin arbiter is a common component for arbitration, would be nice to have in the library

Desired solution

Implement a simple round-robin arbiter

Alternatives considered

No response

Additional details

No response

Support for strobe/enable on read interfaces

Motivation

Some RF implementations allow strobing/byte enable on the read side in addition to the write side. This can be helpful for latch-based memory when writing different portions of a line of data, or for power savings.

Desired solution

Add support for StrobeDataPortInterface on read interfaces of RegisterFile, and any other Memorys where it makes sense.

Alternatives considered

No response

Additional details

No response

Add `extension`s for converting to/from one-hot/binary

Motivation

Since both OneHotToBinary and BinaryToOneHot have one input and one output, it would be nice to access them with an API on top of Logic and LogicValue to convert easily.

Desired solution

Add oneHotToBinary and binaryToOneHot as extensions on Logic and LogicValue.

Alternatives considered

No response

Additional details

No response

Review APB ports that should be optional

Describe the bug

The PNSE port is optional in the APB spec, but not in the ApbInterface. Review the spec and look for any other ports that are optional and ensure they are configurable.

To Reproduce

No response

Expected behavior

No response

Actual behavior

No response

Additional: Dart SDK info

No response

Additional: pubspec.yaml

No response

Additional: Context

No response

LFSR

Motivation

LFSRs are useful as pseudo-random deterministic generators in hardware.

Desired solution

Implement a Linear-feedback shift register (LFSR) in ROHD HCL

Alternatives considered

No response

Additional details

No response

`RegisterFile` is incorrectly using `reset` in `Combinational`

Describe the bug

There's no need to use reset in combinational logic. It is probably a remnant of an old implementation. It should be removed.

To Reproduce

No response

Expected behavior

No response

Actual behavior

No response

Additional: Dart SDK info

No response

Additional: pubspec.yaml

No response

Additional: Context

No response

Use `Logic.or()` instead of custom `OrReduction` in one-hot

Describe the bug

There's already an or reduction via Logic.or() that we should use instead of the OrReduction module.

To Reproduce

No response

Expected behavior

No response

Actual behavior

No response

Additional: Dart SDK info

No response

Additional: pubspec.yaml

No response

Additional: Context

No response

Gray-to-Binary & Binary-to-Gray

Motivation

The Gray Code to Binary Converter is used to convert gray code value to a binary number while binary to Gray Converter convert binary number to gray code.

Desired solution

An implementation in ROHD-HCL

Alternatives considered

No response

Additional details

No response

Sort

Motivation

Sorting is a useful component for the library

Desired solution

A simple first version of sorting to include in the library

Alternatives considered

No response

Additional details

No response

Binary Counter

Motivation

Configurable counters are useful!

Desired solution

  • Reset with reset value
  • Saturation value (maximum value)
  • Saturation behavior (overflow vs. hold at saturated value)
  • Enable (increment) -> when high: increment, when low: don't increment
  • Enable decrement
  • Increment amount
  • Decrement amount
  • number of increments/decrements (different constructors maybe for 1 vs multiple)

Alternatives considered

No response

Additional details

No response

Refractor the confapp to follow MVVM architecture and use Riverpod instead of BLOC

Motivation

The architecture of BLOC is too complicated for confapp. It not that user friendly compared to Provider pattern (Model-View-ViewModel) pattern.

Desired solution

Refractor the state management to Riverpod Provider and Riverpod Generator. We can use MVVM structure as below:

/lib/src:
    - constant/
    - module/
        -  ui/
        - model/
        - view/
        - services/
        - provider/

The pattern above is cleaner and easier to maintain compared to cubit and BLOC.

Alternatives considered

We can just use back BLOC.

Additional details

No response

Find N'th bit=X from start/end

Motivation

Finding the N'th 0 or 1 from the beginning/end of a bus and providing the index

Desired solution

A configurable solution that supports all of these

Alternatives considered

No response

Additional details

No response

Build system is too strict on checking for document links

Describe the bug

When we write documentation we need to refer to HTML files that do not yet exist (e.g., generated schematics) on the deploy site. The generated schematics would likely be part of the add of the same pull request as the referring documentation.

To Reproduce

Create a new html link in a document to an as yet generated schematic in the gen/ area. It may be generatable, but not yet deployed on the production site.

Then push this to a fork and do a pull request. The pull request lint checks will fail.

Expected behavior

Warnings on dead links.

Actual behavior

Failure and job stoppage on 'dead' or really 'not yet alive' links.

Additional: Dart SDK info

No response

Additional: pubspec.yaml

No response

Additional: Context

No response

Parity

Motivation

Parity for error checking

Desired solution

Implement a Parity module, support even and odd

Alternatives considered

No response

Additional details

No response

Pipelined integer multiply

Motivation

Integer multiplication in a pipeline is a nice component for the library

Desired solution

A simple pipelined integer multiplier

Alternatives considered

No response

Additional details

No response

Add a way to put links into the confapp

Motivation

There's sometimes useful information worth adding to the confapp for components, for example:

  • A link to a generated example schematic
  • A link to the original Dart/ROHD source code for the component
  • The component documentation in ROHD-HCL
  • Additional details/documentation/information

Desired solution

Add a way to add links that would appear in the confapp in Configurator. Perhaps make certain links mandatory for all ROHD-HCL components?

Alternatives considered

No response

Additional details

No response

Make it possible to strobe/enable different granularities on memory interfaces

Motivation

Sometimes a strobe/enable is on a byte boundary, but other times it might be per word or some other granularity. It would be nice if the interface supported a configurable granularity instead of just bytes.

Desired solution

Modify StrobeDataPortInterface to support a configurable partitioning of enables other than just bytes.

Alternatives considered

No response

Additional details

No response

Schematic Generation

Motivation

It would be great for our documentation of components to have live schematic views of small parameter forms so that people can visualize how they operate rather than having to read code.

Desired solution

I found a package called d3-hwschematic that does schematic generation for a different language (HWT) written by Nic30. It turns out it uses a form of JSON to drive the d3 graphical kit (based on Eclipse). This is written as an interactive web-page for which you can request any input netlist to be rendered.

However, we can simply have a pre-generated HTML for each component to be embedded in our documentation. We simply need a conversion path: that path is ROHD->Verilog; Yosys->JSON; then yosys.json -> d3.json (converter is in d3-hwschematic distributed Javascript)

The branch https://github.com/intel/rohd-hcl/tree/synthesis has a gh_action/create_htmls.sh that runs on Verilog produced by dart test as an experimental flow. Since there are paths in the HTML, we need to decide where these files will sit in the deployed documentation.

Alternatives considered

Commercial options like nlview are available with a open-source option. It has some incremental expansion operations.

Additional details

This is our PriorityArbiter in schematic form
schematic

CRC

Motivation

Implement a flexible, configurable CRC generator component

Desired solution

See https://en.wikipedia.org/wiki/Cyclic_redundancy_check

The CRC generator should be extremely configurable to generate practically any CRC that may be needed. Some configurability that would be nice:

  • Different ways to construct it (e.g. normal, reversed, reciprocal, reversed reciprocal, list of polynomials, etc.)
  • Pre-configured flavors available for popular CRC polynomials
  • Configurable pipelining (e.g. all in one cycle or pipelined across a configurable number of cycles)

It should be able to both generate and check CRC.

Alternatives considered

No response

Additional details

No response

Add a UI for RTL code generation using Dart web app

Motivation

UI for RTL code generation with interactive customization enhance user experience in using the hardware component library.

Desired solution

  • A UI web interface
  • Generate customization buttons, drag down list for hcl manipulation
  • When system Verilog code generated, allows a copy button to copy the code generated

Alternatives considered

No response

Additional details

No response

Add example stimulus & output, waveform view, and interactive simulation in confapp

Motivation

It would be great to be able to experiment with the functionality of a component live in-browser using the ROHD-HCL web configuration app.

Desired solution

Some thoughts:

  • Configurator can accept a set of "smoke test" type of stimulus, and information about interesting outputs
    • These tests can be used as basic unit tests as well
  • Adding a waveform view of this stimulus to the confapp would be great
    • It could potentially be via wavedrom (https://wavedrom.com/)
    • Another option is to use a from-scratch new flutter-based waveform viewer (e.g. share with rohd devtools extension)
  • Make the simulation interactive: allow the test vectors to be modified live in the browser and update the waves via re-simulation, allowing users to experiment with the functionality of the component.

Alternatives considered

No response

Additional details

No response

Allow JSON configuration to be editable in confapp

Motivation

People may save a configuration a JSON then want to:

  • Restore a configuration in the confapp
  • Modify settings via the JSON rather than the UI (e.g. copy pasting chunks to duplicate stuff)

Desired solution

Make the JSON configuration area editable in the confapp and update the web-app fields as JSON is updated.

Alternatives considered

No response

Additional details

No response

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