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mipi-csi-2's Introduction

MIPI CSI 2 Receiver

Build Status

To-do List

  • Primary format decoding
    • RGB888
    • RGB565
    • YUV422 8-bit
    • RAW8
    • RAW10
  • Tests
    • D-PHY
    • CSI-2
    • Decoding
  • Error-checking and correction
    • Header ECC
    • Footer Checksum
  • N-lane
    • 1 lane
    • 2 lane
    • 3 lane
      • Roadblock: will receive more bytes than the 32-bit buffer
        • Consider long packet with 8 bytes
        • First 3 from header go from corresponding lanes
        • Header byte 4 comes from lane 1, Data byte 1, 2 come from lanes 2 & 3
        • Data byte 3, 4, 5 (!) come from lanes 1, 2, & 3
        • Thus, you are stuck with extra, on the same clock the user gets the buffer
    • 4 lane

Reference Documents

These documents are not hosted here! They are available on Library Genesis and at other locations.

Special Thanks

mipi-csi-2's People

Contributors

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Forkers

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