google / globalfoundries-pdk-ip-gf180mcu_fd_ip_sram Goto Github PK

It would be good to be able to reproduce the .lef and .cdl files from the .gds file using Magic.

DRC violations in GF018_5VGreen_SRAM_1P_256x8M8WM1 vs. documented rule in the design manual

PL.12

The repository should contain example of how to do a spice simulation of the SRAM macro using common open source tools like xyce / ngspice.

The repository should contain example of how to do a digital simulation of the SRAM macro using common open source tools like Verilator.

Expected Behavior

gf180mcu_fd_ip_sram__sram256x8m8wm1 should have A[7:0]
gf180mcu_fd_ip_sram__sram512x8m8wm1 should have A[8:0]
gf180mcu_fd_ip_sram__sram64x8m8wm1 should have A[5:0]

Actual Behavior

in documentation all sram modules have A[6:0] as address description so it's correct only for sram128x8 (this is only documentation issue - in verilog everything looks ok)

Steps to Reproduce the Problem

Look into these 3 CSV files:
cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/1_pins_desc.csv:A[6:0],Input,"Address Input. This Address input port is used to
cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/1_pins_desc.csv:A[6:0],Input,"Address Input. This Address input port is used to
cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/1_pins_desc.csv:A[6:0],Input,"Address Input. This Address input port is used to

Specifications

• Version:
• Platform: