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SRAM macros created for the GF180MCU provided by GlobalFoundries.

Home Page: https://gf180mcu-pdk.rtfd.io

License: Apache License 2.0

Verilog 100.00%

asic globalfoundries eda ip openroad pdk sram 180nm gf180mcu

globalfoundries-pdk-ip-gf180mcu_fd_ip_sram's Introduction

GlobalFoundries 180um SRAM macros

This repository contains the "SRAM macros" as part of Google's open source PDK for GlobalFoundries 180nm MCU process node.

License

The GF180MCU PDK is released under the Apache 2.0 license.

The copyright details (which should also be found at the top of every file) are;

Copyright 2022 GlobalFoundries PDK Authors

Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at

    http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.

globalfoundries-pdk-ip-gf180mcu_fd_ip_sram's People

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var52yt mabrains mithro loesterfranco abdelazeem201

globalfoundries-pdk-ip-gf180mcu_fd_ip_sram's Issues

Incorrect Address width in descriptions for 3 SRAM modules

Expected Behavior

gf180mcu_fd_ip_sram__sram256x8m8wm1 should have A[7:0]
gf180mcu_fd_ip_sram__sram512x8m8wm1 should have A[8:0]
gf180mcu_fd_ip_sram__sram64x8m8wm1 should have A[5:0]

Actual Behavior

in documentation all sram modules have A[6:0] as address description so it's correct only for sram128x8 (this is only documentation issue - in verilog everything looks ok)

Steps to Reproduce the Problem

Look into these 3 CSV files:
cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/1_pins_desc.csv:A[6:0],Input,"Address Input. This Address input port is used to
cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/1_pins_desc.csv:A[6:0],Input,"Address Input. This Address input port is used to
cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/1_pins_desc.csv:A[6:0],Input,"Address Input. This Address input port is used to

Specifications

Version:
Platform:

PL.12

Add test benches and example (spice / analog) simulations for the .cdl files

The repository should contain example of how to do a spice simulation of the SRAM macro using common open source tools like xyce / ngspice.

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