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picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

picosha2

a header-file-only, SHA256 hash generator in C++

picsimlab

PICsimLab - Programmable IC Simulator Laboratory

platform_nangate45

The directory flow/platforms/nangate45 from OpenROAD-flow, standalone, to avoid including the full OpenRoad-flow as a submodule

plic

Platform Level Interrupt Controller

projects

pybison

Use Bison directly from Python

pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

qemu

QEMU RISC-V Repo

qtcverilog

This is a stand-alone Verilog IDE derived from a QtCreator 3.6.1 subset featuring the VerilogCreator plugin

quadcopter

Arduino based Quadcopter

quicklogic-fpga-toolchain

Open Source FPGA toolchain and documentation for QuickLogic devices and eFPGA IP

rattlesnake

PulseRain Rattlesnake - RISCV RV32IMC Soft CPU

ravenoc

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

reactiveui

An advanced, composable, functional reactive model-view-viewmodel framework for all .NET platforms that is inspired by functional reactive programming. ReactiveUI allows you to abstract mutable state away from your user interfaces, express the idea around a feature in one readable place and improve the testability of your application.

reindeer

PulseRain Reindeer - RISCV RV32I[M] Soft CPU

resea

A microkernel-based hackable operating system.

ridecore

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

riot

RIOT - The friendly OS for IoT

ripes

A graphical 5-stage RISC-V pipeline simulator & assembly editor

riscv

RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU

riscv-1

RISC-V CPU Core (RV32IM)

riscv-asm-manual

RISC-V Assembly Programmer's Manual

riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

riscv-crypto

RISC-V cryptography extensions standardisation work.

riscv-debian

A set of scripts to build a (somewhat) working Debian image for RISC-V.

riscv-dv

riscv-emu

RISC-V emulator that is written in Rust. Support Linux, xv6, NuttX, FreeRTOS, Zephyr OS etc.

riscv-isa-extension-for-sm4

RISC-V instruction set extensions for SM4 block cipher

riscv-multi-cycle

WIP - A multi-cycle implementation of the RISCV rv32ui architecture.