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muraxarduino

A version of f32c/arduino that works with the SpinalHDL Vexriscv Murax SoC

my_fcp

fcp

mynewt-core

An OS to build, deploy and securely manage billions of devices

nandflashcontroller

AXI Interface Nand Flash Controller (Sync mode)

nanorv32

A small 32-bit implementation of the RISC-V architecture

neorv32

A small, customizable and open-source full-scale 32-bit RISC-V rv32imcu + privileged architecture CPU and SoC written in platform-independent VHDL.

ngspice

nmigen-tutorial

A tutorial for using nmigen

nodenetwork

A C# library with a WPF node editor component based on ReactiveUI

nyuziprocessor

GPGPU microprocessor architecture

oh

Silicon proven Verilog library for IC and FPGA designers

old-openrisc-svn

Copy of the old OpenCores OpenRISC Subversion

oldland-cpu

Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools

open_pdks

PDK installer for open-source EDA tools and toolchains. Distributed with a setup for the Google/SkyWater 130nm process.

openbsd-riscv-notes

openc910

OpenXuantie - OpenC910 Core

openfpga

An Open-source FPGA IP Generator

openlane

OpenLANE is an automated RTL to GDSII flow based on several components including OpenRoad, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

openmsp430

The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.

openocd_riscv

Spen's Official OpenOCD Mirror

openpiton

The OpenPiton Platform

openram

An open-source static random access memory (SRAM) compiler.

openroad-example

Hello World

opensparc-fpu

ASIC Design of the openSPARC Floating Point Unit

opentimer

A High-performance Timing Analysis Tool for VLSI Systems

opentitan

OpenTitan: Open source silicon root of trust

openwifi

open-source IEEE802.11/Wi-Fi baseband chip/FPGA design

orca

RISC-V by VectorBlox

panologic-g2

Pano Logic G2 Reverse Engineering Project

patmos

Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project