curliph,github

gdbstub-1

A simple, dependency-free GDB stub that can be easily dropped in to your project.

GDS3D is an application that can interpret so called IC layouts and render them in 3D. The program accepts standard GDSII files as input data. Along with the layout file, it requires a so called process definition file which contains the 3D parameters of the process being used. These files combined allow the program to create a 3D representation of the layout, where the user has full, real time control over the camera position and angle, much like in a 3D video game. An other repo (https://github.com/skuep/GDS3D) as the same source and add few improvement like compression with server/client process. This release add two major feature with are assembly and export 3D model for GMSH. Assembly: this mean it’s possible to merge multi GDS (with different technologies) I also try to improve net highlight.

gen_amba

AMBA bus generator including AXI, AHB, and APB

gen_amba_2021

AMBA bus generator including AXI4, AXI3, AHB, and APB

glasgow

Scots Army Knife for electronics

hadbadge2019_fpgasoc

FPGA SoC code and application example for Hackaday Supercon 2019 badge

hdl

HDL libraries and projects

hl5

A 32-bit RISC-V Processor Designed with High-Level Synthesis

html-renderer

Cross framework (WinForms/WPF/PDF/Metro/Mono/etc.), Multipurpose (UI Controls / Image generation / PDF generation / etc.), 100% managed (C#), High performance HTML Rendering library.

icc2_workshop_collaterals

This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efabless Corp. Pvt. Ltd. VSD has not checked functionality for these collaterals, so please do not expect a functionality bug fix. These are used purely for PNR workshops and trainings

ice40linux

Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker

icicle

32-bit RISC-V system on chip for iCE40 and ECP5 FPGAs

jop

JOP is a Java processor for real-time systems

jtag_dpi

JTAG DPI module for SystemVerilog RTL simulations

jtag_dpi-1

JTAG DPI module for OpenRISC simulation with Verilator

jtag_uart_example

Mini CPU design with JTAG UART support

jtag_vpi

TCP/IP controlled VPI JTAG Interface.

juicevm

The juice virtual machine was born in 2020, with the goal of realizing the smallest virtual machine of RISC-V that can run the latest kernel mainline. At the beginning of the design, it runs on a platform with only 100 KB of RAM, which does not exceed the number of C99. Three-party dependence.

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