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View Code? Open in Web Editor NEWOverview The objective of this project is to design object specified microprocessor and a Central Processing Unit in order to downscale an image. As steps of above task, we have to simulate it using the Verilog hardware description language, and finally to implement it in hardware using programmable logic device such as FPGA (Field Programmable Gate Array). This document describes all the steps we followed in the microprocessor and CPU design, the test codes used to verify it, and the physical hardware implementation.