rookiephysicist,github

5-stage-pipelined-mips32-risc-processor-design-on-verilog

This repository contains the details and the code for the MIPS32 ISA based RISC Processor, which is implemented in 5 stage pipelined configuration.

about-go-to-femto-v-tutorials-blink-to-risc-v-for-tutorial-on-risc-v-processo

Go To Femto-V/ Tutorials / Blink to RISC-V for tutorial on RISC-V processor

ahb-to-apb-bridge

The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB.

elevator-control-system-using-verilog

Elevator Controller for 60 floors building using Verilog code

fpga-uart-tx-rx-better-

Basic UART TX/RX module for FPGA

fpga_fft_spectrum_analyzer

This project implements the fft algorithm on the Spartan 3E FPGA (Papillio One Platform) which in turn is used as a spectrum analyzer with some added hardware (e.g. ADC).

implementation-of-cdma-transmitter-and-receiver-using-intel-de2i-150-fpga-board

Using the Quartus II software, an OFDM transmitter system was designed and implemented on Intel DE2i-150 board. Here QPSK is used as the digital modulation technique and Altera FFT MegaCore Function has been used to implement the Inverse Fast Fourier Transform block. The output of the OFDM transmitter is displayed on the monitor by implementing VGA

lifi

The implementation of LiFi protocol on the BASYS3 Xilinx Artix-7 board using VHDL.

lifi-ofdm

Lot of C in it. May be useful in future.

position_detection

📌 The idea of this project is to build a system that uses the existing lights to detect the location of a user within an indoor environment. For this, we can use Visible Light Communication (VLC) technology. The basic concept is to have four LEDs transmitting their IDs one after the other at fixed intervals.

processor-design-and-implementation-on-a-fpga

Overview The objective of this project is to design object specified microprocessor and a Central Processing Unit in order to downscale an image. As steps of above task, we have to simulate it using the Verilog hardware description language, and finally to implement it in hardware using programmable logic device such as FPGA (Field Programmable Gat

uart-communication-link-on-a-fpga-using-verilog-hdl

This post is regarding a HDL implementation of a UART(Universal Asynchronous Receiver Transmitter) for one of our university fourth semester projects.For the project we were supposed to implement a UART link for a FPGA development board using Verilog as the HDL and send some data to another FPGA development board which also have a UART implementati

rookiephysicist Goto Github PK

rookiephysicist's Projects

5-stage-pipelined-mips32-risc-processor-design-on-verilog

about-go-to-femto-v-tutorials-blink-to-risc-v-for-tutorial-on-risc-v-processo

ahb-to-apb-bridge

elevator-control-system-using-verilog

fpga-uart-tx-rx-better-

fpga_fft_spectrum_analyzer

implementation-of-cdma-transmitter-and-receiver-using-intel-de2i-150-fpga-board

lifi

lifi-ofdm

position_detection

processor-design-and-implementation-on-a-fpga

uart-communication-link-on-a-fpga-using-verilog-hdl

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