a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communication and Crypto applications
I trying to run the DsplpTest for the Fir test. but the coeffs is not change when I modigy the fir configuration.
val coeffLengths = Seq(19)
val coeffs = coeffLengths.map(
designFilter(, Seq(80 MHz), 240 MHz, "lowpass").map(.toDouble)
)
about the consol :
C:\Anaconda3\python.exe C:\project\SpinalHDL\Chainsaw\goldenModel\utils\design_filter.py 19 [8.0E7] 2.4E8 lowpass
python output:
[INFO ]: Number of inter-op threads is 6
[INFO ]: Number of intra-op threads is 6
I trying to run the design_filter.py seprately. It's ok.