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1st-claas

Framework for developing and deploying FPGA logic in the cloud as a microservice for web and cloud applications

advanced-embedded-system-design-flow-on-zynq

altera_cookbook

Altera Advanced Synthesis Cookbook 11.0

async-rdma

avsdpll_3v3

This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—40MHZ to 100MHZ at 1.8v)IP worked on in the VSD Online Internship.

aws-f1-workshop_cn

axi-dma

axi_spec_chinese

AXI协议规范中文翻译版

aya

Aya is an eBPF library for the Rust programming language, built with a focus on developer experience and operability.

bcc-sys

blake2b_compress

verilog implementation of blake2b_compress

blue-rdma

RoCEv2 hardware implementation in Bluespec SystemVerilog

blueaxi4

bluebasics

bluelib

Miscellaneous components for bluespec

bluespec-tutorials

FPGA coding with bluespec and connectal framework

bluestuff

A Bluespec SystemVerilog library of miscellaneous components

bsc

Bluespec Compiler (BSC)

bsv_lab_docs

caravel_user_project

https://caravel-user-project.readthedocs.io

caribou

Caribou: Distributed Smart Storage built with FPGAs

ch34x-usb-serial-linux-driver

chainsaw

a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communication and Crypto applications

clash-merlin

connectal

Connectal is a framework for software-driven hardware development.

corundum

Open source, high performance, FPGA-based NIC

crd-operator-example

csi

darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

data-sync