pwang7 Goto Github PK

uart-vcs

ucr_ee260_lab

UC Riverside EE 260 Winter 2017: Advanced VLSI Design

utilities

verilog-cam

Verilog Content Addressable Memory Module

verilog-ethernet

Verilog Ethernet components for FPGA implementation

verilog-pcie

Verilog PCI express components

vexriscvpipelinedemo

vitis_with_100gbps_tcp-ip

100 Gbps TCP/IP stack for Vitis shells

vivado-build-system

Vivado build system

vivado-library

vivado_batch_mode_tool

A tool for those who want to use Vivado's batch mode more easily

vsdbabysoc

VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.

vsdflow

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.

vsdfpga

Implementation of Mixed Signal SoC (RISCV based Core + PLL) on FPGA

vsdpcvrd

Performance characterization for VSD BabySoC comprising of RISC-V core, PLL and DAC

xilinx-fpga-pcie-xdma-tutorial

Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核

xilinx-workshops

Updated version of the XUP Workshops

xline

xup_vitis_network_example

VNx: Vitis Network Examples

zynq-axi-dma-sg

Simple C snippet to transfer DMA memory with scatter/gather on a Zynq 7020