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verilog-axis

Verilog AXI stream components for FPGA implementation

verilog-ethernet

Verilog Ethernet components for FPGA implementation

verilog-pcie

Verilog PCI express components

veripass

victima

Source code and scripts for Artifact Evaluation of the upcoming MICRO 2023 paper Victima.

vitis_accel_examples

Vitis_Accel_Examples

vitis_libraries

Vitis Libraries

vlsi-tic-tac-toe

Tic Tac Toe with Reinforcement Learning implementation using Verilog (Hardware design)

xfopencv

xstore

Fast RDMA-based Ordered Key-Value Store using Remote Learned Cache

xup-vitis-ai-tutorial

Hands-on experience using Vitis AI with Xilinx FPGA hardware

ycsb

Yahoo! Cloud Serving Benchmark

zcu102-ethernet

Ethernet Example Projects targeting the Xilinx ZCU102 evaluation board. This repository replaces XAPP1305.