ultraembedded / core_soc Goto Github PK

Hi @ultraembedded,

I am using spi_lite in my project with a RISC-V based Processor. I am getting some errors while communicating through spi.
I am using spi master with soft processor in FPGA side and esp8266 as slave for communication. When I send a block of character (string) from master then at slave side sometimes I get exact string and sometime a garbage value is read.

Also kindly do let me know that how to did you verified this core in simulation and what type of slave device you used for verification on board.

By the way I have used your uart ip it working perfectly thank you very much for providing such sharing such amazing work online. I hope you'll help in making spi working fine. waiting for your response.