chisel-awl's People
chisel-awl's Issues
Refactor
With upcoming integration with ADC/DAC components, we should refactor this into serial/adc/dac packages and rename to 'chisel-awl' (Analog Widget Library).
Add near and far-end loopback debug modules
Rename to "chis-awl"?
Create a Bert Unit Test
HBWIF Simulation Deserialization Bug
HBWIF simulation is broken (specifically in BEAGLE). If I remember correctly this was found in the deserializer? This is mainly just a reminder to re-look at the simulation when there is a bit more time (Low-priority).
Can chisel do 1-indexed Vecs?
This would make the DFE tap Vecs a lot cleaner
Resets
Need to separate out the transceiver reset and the digital reset.
Negotiate bitwidths with far-side
Increase the buffer to some pre-specified width, then compute header sizes based on pre-negotiated commands. This would likely involve some set of internal registers that are writeable by the far-end using a new control sequence
Add pattern/snapshot mems to the data interface
Right now we can take a snapshot of the serial RX interface or send a pattern to the serial TX interface, but it would also be good to be able to "replicate" the serial interface to the downstream interface.
TileLink Backend Features
Add the ability to shut off new requests and report when no requests are outstanding, which will enable gracefully turning off the memory channel mode.
Pattern memory MMIO address mangling
The MMIO addresses are allocated by the stringly-sorted names rather than a logical ordering. This causes pattern memories (and snapshots, presumably) for a 16-word configuration to be allocated in the order <0, 1, 10, 11, 12, 13, 14, 15, 2, 3, 4, 5, 6, 7, 8, 9> instead of numerically.
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