Topic: dram Goto Github
Some thing interesting about dram
Some thing interesting about dram
dram,MIPS simulator, which implements reordering of DRAM requests during runtime to reduce the clock cycles during execution
User: 5ayam5
dram,A multi-core MIPS simulator with Memory Request Manager for reordering DRAM requests to maximise throughput
User: 5ayam5
dram,MIPS ISA simulator which implements non-blocking DRAM access
User: 5ayam5
dram,A Multi-core MIPS ISA, with MRM and DRAM, Simulator. Prints what is happening in every clock cycle and the final content of registers and DRAM.
User: aayushgoyal443
dram,Improving DRAM Reliability and Performance On-Demand via Coherent Replication [ISCA 2021]
User: adarshpatil
Home Page: https://adar.sh/dve
dram,HAShCache + Intergrated CPU/GPU system simulation setup
User: adarshpatil
dram,A 1MB chip RAM expansion for the A500+
User: blark
dram,This is a repository for the ParaMonte library examples. For more information, visit:
Organization: cdslaborg
Home Page: https://www.cdslab.org/paramonte
dram,BEER determines an ECC code's parity-check matrix based on the uncorrectable errors it can cause. BEER targets Hamming codes that are used for DRAM on-die ECC but can be extended to apply to other linear block codes (e.g., BCH, Reed-Solomon). BEER is described in the 2020 MICRO paper by Patel et al.: https://arxiv.org/abs/2009.07985.
Organization: cmu-safari
dram,Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of the CLR-DRAM architecture and the baseline architecture used in our ISCA 2020 paper "Luo et al., CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off": https://people.inf.ethz.ch/omutlu/pub/CLR-DRAM_capacity-latency-reconfigurable-DRAM_isca20.pdf
Organization: cmu-safari
dram,This repository provides characterization data collected over 96 DDR3 SO-DIMMs, related to the following paper: Lee et al., "Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms", SIGMETRICS 2017. https://people.inf.ethz.ch/omutlu/pub/DIVA-low-latency-DRAM_sigmetrics17-paper.pdf
Organization: cmu-safari
dram,DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art DDR4 modules of different form factors. Five prototypes are available on different FPGA boards. Described in our preprint: https://arxiv.org/pdf/2211.05838.pdf
Organization: cmu-safari
dram,A survey of manufacturer-provided DRAM operating parameters and timings as specified by DRAM chip datasheets from between 1970 and 2021. This data and its analysis are described in the 2022 paper by Patel et al.: https://arxiv.org/abs/2204.10378
Organization: cmu-safari
dram,Experimental study and analysis on the effect of using a wide range of different supply voltage values on the reliability, latency, and retention characteristics of DDR3L DRAM SO-DIMMs
Organization: cmu-safari
Home Page: https://arxiv.org/abs/1705.10292
dram,DRAM error-correction code (ECC) simulator incorporating statistical error properties and DRAM design characteristics for inferring pre-correction error characteristics using only the post-correction errors. Described in the 2019 DSN paper by Patel et al.: https://people.inf.ethz.ch/omutlu/pub/understanding-and-modeling-in-DRAM-ECC_dsn19.pdf.
Organization: cmu-safari
dram,HARP is a memory error profiling algorithm (i.e., for identifying error-prone cells) designed for use with memory chips that use on-die error-correcting codes (ECC). This tool uses Monte-Carlo simulation to evaluate HARP and other error profilers. HARP and this tool are described in the 2021 MICRO paper by Patel et al.: https://arxiv.org/abs/2109.12697.
Organization: cmu-safari
dram,Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
Organization: cmu-safari
Home Page: https://arxiv.org/abs/2308.11030
dram,REGA Model (REM), an accurate DRAM model.
Organization: comsec-group
dram,A PIM instrumentation, compilation, execution, simulation, and evaluation repository for BLIMP-style architectures.
User: dovedevic
dram,Design of a simulator of a multi-core processor and DRAM for a subset of MIPS instruction set architecture in C++. Course Project of COL216: Computer Architecture taught in Second Sem, 2020-21 at IIT Delhi
User: gauravjain28
dram,DRAM Request Manager for Multicore Processors
User: guptaaniket261
dram,Generic FPGA SDRAM controller, originally made for AS4C4M16SA
Organization: hdl-util
Home Page: https://purisa.me/blog/mipi-camera-progress/
dram,An FPGA working in serial with HDMI, for some real live video modifications
User: jakubkajzer
dram,A library that allows the Arduino UNO to read/write to old DIP-style DRAM chips
User: johnzl-777
dram,Behavioral architecture of a read/write cycle controller for a DRAM chip.
User: jtsimons
dram,Cross-platform CLI and Python drivers for AIO liquid coolers and other devices
Organization: liquidctl
dram,MCMC toolbox for Matlab
User: mjlaine
Home Page: https://mjlaine.github.io/mcmcstat/
dram,Repo for my master thesis
User: namhogim
dram,A curated list of awesome Rowhammer papers, tools, and info resources. 👉 Content coming soon, stay tuned!
User: pjattke
dram,**No Longer Maintained** Official RAMCloud repo
Organization: platformlab
Home Page: https://ramcloud.atlassian.net/wiki/spaces/RAM/overview
dram,Commodore C386SX-LT 2MB memory module schematics
User: ppieczul
dram,Implementation of flush + reload attack to extract private key from the GnuPG implementation of RSA.
User: saiteja-talluri
dram,Decay-based DRAM PUF for the Raspberry Pi 3B+ implemented on top of rpi-open-firmware
User: thexxturboxx
Home Page: https://doi.org/10.1145/3458824
dram,DRAMSim2: A cycle accurate DRAM simulator
Organization: umd-memsys
Home Page: http://www.ece.umd.edu/~blj/papers/cal10-1.pdf
dram,Bayesian Inference. Parallel implementations of DREAM, DE-MC and DRAM.
User: wgurecky
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