tommythorn Goto Github PK

tt06-memory

Memory in one Tiny Tapeout tile

tt06-ncl-lfsr

NCL LFSR

tt06-tommythorn-4b-cpu

Silly 4b CPU v2

tt07-memory

A very crazy attempt at creating memory from a22o gates (smaller than latches)

tt07-more-ncl-experiments

More simple NCL circuits

tt08-maxbw

Testbench and [partial] proof-of-concept of the MaxBW core-uncore interconnect

verilator-demo

A very simple example of how to use Verilator

verilog-sim-bench

Verilog simulation workload extracted from Reduceron

virtual-nascom

SDL-based Nascom 2 emulator

waves

Sandbox for ways to visualize waves in the terminal

wrapped_rgb_mixer

write-you-a-haskell

Building a modern functional compiler from first principles. (http://dev.stephendiehl.com/fun/)

yari

YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includes a complete SoC, simulator, GDB stub, scripts, and various examples.

yarvi

Yet Another RISC-V Implementation

yarvi3