tommythorn Goto Github PK

kintex-7-stlv7325t-board-files

kinto

A better Linux & Windows keyboard layout for professional mac users

lisp

A version of John McCarthy's tiny Lisp (in C) with added CDR-coding

multisim

MultiSim is Yet Another CPU Simulator which purpose in life is to allow easy experimentation with various implementation strategies, such as superscalar in-order, sscalar out-of-order, speculative sscalar out-of-order, etc.

nascomhomepage.com

Mirror of nascomhomepage.com

ncl_sandbox

Is a collection of NULL Convention Logic (NCL) circuits and libraries written in Verilog to provide the experience of logically determined design in a familiar context. The tools used are Icarus verilog and gtkwave.

orangecrab

ECP5 breakout board in a feather physical format

orangecrab_hello

Simple OrangeCrab Verilog design using LED and serial IO

paperlike-raspberry-pi-4

How to use a Dasung Paperlike HD-F, HD-FT, and Paperlike 253 with Raspberry Pi 4 [and other hosts?]

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

previous-code

Full mirror of the Previous NeXT computer emulator's SVN repository http://previous.alternative-system.com (including SVN's awkward branches)

reduceron

FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.

rgb_mixer

riscv-compliance

riscv-debug-spec

Working Draft of the RISC-V Debug Specification Standard

riscv-fesvr

RISC-V Frontend Server

riscv-isa-manual

RISC-V Instruction Set Manual

riscv-opcodes

RISC-V Opcodes

riscv-plic-spec

PLIC Specification

riscv-tests

riscv-tools

RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)

rust-verilog-cosim

Small example of how to co-simulate a Rust model against a Verilog implementation, using Verilator

sdcc-nascom

crt0 and Makefile to enable SDCC to produce code for Nascom 2

sesc-mirror

Unadulted git mirror of the SESC CVS repo on https://sourceforge.net/p/sesc/code/sesc

silly-little-pl

Fun with Dragonbook/Wirth-style compilers

spleentt-5x8-font

Tiny 5x8 bitmap font based on spleen and creep, useful for low-resolution displays

tinytapeout-4-bit-cpu

A design for TinyTapeout

tinytapeout02-chacha20

Can we fit a chacha20 encryption core on Tiny Tapeout?

tommythorn.github.io

verilator-demo

A very simple example of how to use Verilator