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jtag_verliog_rtl's Introduction

Hi 👋, I'm Teekam Chand Khandelwal

Teekam chand khandelwal 👨‍💻

About

  • 💡 :I like to explore new technologies and creating projects(Front-end VLSI).
  • 🔭 I’m currently working on: Verification of communication protocoal and Irrigation Controller using Verilog Based on Fuzzy logic and some projects of RTL design.
  • 🌱 I’m currently learning: I'm on track for learning more about System verilog Assertion,code coverage and UVM
  • 📫 How to reach me: You can shoot me an email at [email protected]! I'll try to respond as soon as I can
  • 😄 Pronouns: He/ His/ Him 😇

teekamkhandelwal

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Teekam Chand Khandelwal

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jtag_verliog_rtl's Issues

License Question

Hello, I see on the License file that the folder is under Apache license but I don't see that on the headers of the rtl code and the test bench. I just want to be sure that I can use them under the Apache 2.0 License conditions.

Thank you very much

LM. LAURENT

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