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Designed AHB to APB Bridge Controller using Verilog and simulated it on ModelSIM
Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
AHB3-Lite Interconnect
Asynchronous fifo in verilog
Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.
AXI4 and AXI4-Lite interface definitions
Verilog program
Booth encoded Wallace tree multiplier
Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
AHB DMA 32 / 64 bits
Hardware implementation of Error-Correction Code in Verilog
模拟spi驱动w25q32 flash存储器
异步FIFO的内部实现
Use Verilog to complete the design of various digital circuits, including common interfaces, such as UART, Bluetooth, IIC, AMBA, etc. It also includes various common circuits, such as FIFO, RAM, state machine, and so on. All designs have been validated by Testbench and FPGA functions.
Control and Status Register (CSR) subsystem accessible through JTAG
jtag tap_controller_fsm Verilog code
Easy-to-use JTAG TAP and Debug Controller core written in Verilog
MEMORY BUILT-IN SELF TESTING CODE IN VERILOG
A Flyweight MBIST Block - FPGA synthesizable, Multi-algorithm integrated
apb-uart
Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder
AXI Interface Nand Flash Controller (Sync mode)
An FPGA-tested, Verilog 16-bit logic analyzer
SDAccel Examples
ITMO SystemC & Verilog assignments - AMBA AHB and SPI
SPI Master for FPGA - VHDL and Verilog
SPI Slave for FPGA in Verilog and VHDL
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Open source projects and samples from Microsoft.
Google ❤️ Open Source for everyone.
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Data-Driven Documents codes.
China tencent open source team.