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zjed's Projects

asynchronous_fifo icon asynchronous_fifo

Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.

ecc_hardware icon ecc_hardware

Hardware implementation of Error-Correction Code in Verilog

ic_system_design icon ic_system_design

Use Verilog to complete the design of various digital circuits, including common interfaces, such as UART, Bluetooth, IIC, AMBA, etc. It also includes various common circuits, such as FIFO, RAM, state machine, and so on. All designs have been validated by Testbench and FPGA functions.

jtag-base icon jtag-base

Control and Status Register (CSR) subsystem accessible through JTAG

jtaglet icon jtaglet

Easy-to-use JTAG TAP and Debug Controller core written in Verilog

mbist icon mbist

MEMORY BUILT-IN SELF TESTING CODE IN VERILOG

mbist-verilog icon mbist-verilog

A Flyweight MBIST Block - FPGA synthesizable, Multi-algorithm integrated

multiplier16x16 icon multiplier16x16

Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder

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