t-head-semi / openc910 Goto Github PK

Please provide the documentation for XIE and can anyone verify whether Vector instructions are supported by openc910

The binary in smart_run/tests/bin/Srec2vmem is not executable after "git clone"
During compile the work/*.log shows the following:
make: execvp: ../tests/bin/Srec2vmem: Permission denied

Suggest adding "chmod a+rx" in Makefile/Setup scripts, or using python script instead.
See: T-head-Semi/wujian100_open#46

Also where is source to Srec2vmem?

The discussion group is full(1000/1000). Can you set up a new one?

Sorry to bother but I couldn't find code or doc for multi-core usage. Anyone knows how to run.

comment is "#"

In the Makefile in smart_run directory, the last five line lack the other half of "
@echo " make runcase CASE=coremark SIM=verilator THREADS=8 : run case 'coremark' without dump(by verilator) with 8 threads;
@echo " make cleanVerilator : clean the verilator generated file before Verilator operations;
@echo " make compile SIM=verilator DUMP=on THREADS=8 : run compile with dump (by Verilator with dump) with 8 threads;
@echo " make buildVerilator : run build executable file with Verilator;
@echo " make runVerilator : run simulation file with Verilator;

麻烦释放一个新群

https://github.com/T-head-Semi/openc910/blob/main/C910_RTL_FACTORY/gen_rtl/iu/rtl/multiplier_65x65_3_stage.v#L172 Here in the instance, the parameter part should have () at both sides of the number, like the code above.

Without these (), yosys will throw an error for the code, and the Verilog standard requires #() to be a part of parameter_value_assignment .

I'm using the XuanTie C910 simulation and always get an error simulation finished with error. Does the great god know what the reason is?

How to generate tarmac file for xuantie 908/910 to see the run status？

unable to compile the openc910 using OpenLANE getting errors in verilator the errors - %Error: //openlane/designs/RISCV_CPU/src/ct_ifu_icache_data_array0.v:264:3: syntax error, unexpected '.'
264 | .A (ifu_icache_index[WIDTH:3] ),
| ^
%Error: //openlane/designs/RISCV_CPU/src/ct_lsu_st_dc.v:1368:33: Define or directive not defined: 'VA_WIDTH' : ... Suggested alternative: 'PA_WIDTH'
1368 | assign st_dc_had_bkpta_addr[8-1:VA_WIDTH] = mmu_lsu_mmu_en | ^~~~~~~~~ %Error: //openlane/designs/RISCV_CPU/src/ct_lsu_st_dc.v:1368:42: syntax error, unexpected ']', expecting TYPE-IDENTIFIER 1368 | assign st_dc_had_bkpta_addr[8-1:VA_WIDTH] = mmu_lsu_mmu_en
| ^
%Error: //openlane/designs/RISCV_CPU/src/ct_lsu_st_dc.v:1369:22: Define or directive not defined: 'VA_WIDTH' : ... Suggested alternative: 'PA_WIDTH'
1369 | ? {8-VA_WIDTH{had_yy_xx_bkpta_base[VA_WIDTH-1]}}
| ^~~~~~~~~
%Error: //openlane/designs/RISCV_CPU/src/ct_lsu_st_dc.v:1369:53: Define or directive not defined: 'VA_WIDTH' : ... Suggested alternative: 'PA_WIDTH'
1369 | ? {8-VA_WIDTH{had_yy_xx_bkpta_base[VA_WIDTH-1]}}
| ^~~~~~~~~
%Error: //openlane/designs/RISCV_CPU/src/ct_lsu_st_dc.v:1370:44: Define or directive not defined: 'VA_WIDTH' : ... Suggested alternative: 'PA_WIDTH'
1370 | : had_yy_xx_bkpta_base[8-1:VA_WIDTH]; | ^~~~~~~~~ %Error: //openlane/designs/RISCV_CPU/src/ct_lsu_st_dc.v:1372:29: Define or directive not defined: 'VA_WIDTH'
: ... Suggested alternative: 'PA_WIDTH' 1372 | assign st_dc_had_bkpta_addr[VA_WIDTH-1:0] = {had_yy_xx_bkpta_base[VA_WIDTH-1:8], | ^~~~~~~~~ %Error: //openlane/designs/RISCV_CPU/src/ct_lsu_st_dc.v:1372:68: Define or directive not defined: 'VA_WIDTH'
: ... Suggested alternative: 'PA_WIDTH' 1372 | assign st_dc_had_bkpta_addr[VA_WIDTH-1:0] = {had_yy_xx_bkpta_base[VA_WIDTH-1:8], | ^~~~~~~~~ %Error: //openlane/designs/RISCV_CPU/src/ct_lsu_st_dc.v:1376:33: Define or directive not defined: 'VA_WIDTH'
: ... Suggested alternative: 'PA_WIDTH' 1376 | assign st_dc_had_bkptb_addr[8-1:VA_WIDTH] = mmu_lsu_mmu_en
| ^~~~~~~~~
%Error: //openlane/designs/RISCV_CPU/src/ct_lsu_st_dc.v:1376:42: syntax error, unexpected ']', expecting TYPE-IDENTIFIER
1376 | assign st_dc_had_bkptb_addr[8-1:VA_WIDTH] = mmu_lsu_mmu_en | ^ %Error: //openlane/designs/RISCV_CPU/src/ct_lsu_st_dc.v:1377:22: Define or directive not defined: 'VA_WIDTH'
: ... Suggested alternative: 'PA_WIDTH' 1377 | ? {8-VA_WIDTH{had_yy_xx_bkptb_base[VA_WIDTH-1]}} | ^~~~~~~~~ %Error: //openlane/designs/RISCV_CPU/src/ct_lsu_st_dc.v:1377:53: Define or directive not defined: 'VA_WIDTH'
: ... Suggested alternative: 'PA_WIDTH' 1377 | ? {8-VA_WIDTH{had_yy_xx_bkptb_base[VA_WIDTH-1]}} | ^~~~~~~~~ %Error: //openlane/designs/RISCV_CPU/src/ct_lsu_st_dc.v:1378:44: Define or directive not defined: 'VA_WIDTH'
: ... Suggested alternative: 'PA_WIDTH' 1378 | : had_yy_xx_bkptb_base[8-1:VA_WIDTH];
| ^~~~~~~~~
%Error: //openlane/designs/RISCV_CPU/src/ct_lsu_st_dc.v:1380:29: Define or directive not defined: 'VA_WIDTH' : ... Suggested alternative: 'PA_WIDTH'
1380 | assign st_dc_had_bkptb_addr[VA_WIDTH-1:0] = {had_yy_xx_bkptb_base[VA_WIDTH-1:8],
| ^~~~~~~~~
%Error: //openlane/designs/RISCV_CPU/src/ct_lsu_st_dc.v:1380:68: Define or directive not defined: 'VA_WIDTH' : ... Suggested alternative: 'PA_WIDTH'
1380 | assign st_dc_had_bkptb_addr[VA_WIDTH-1:0] = {had_yy_xx_bkptb_base[VA_WIDTH-1:8],
| ^~~~~~~~~
%Error: //openlane/designs/RISCV_CPU/src/ct_lsu_st_dc.v:1384:25: Define or directive not defined: 'VA_WIDTH' : ... Suggested alternative: 'PA_WIDTH'
1384 | assign st_dc_bkpta_addr[VA_WIDTH-1:0] = {st_dc_va[VA_WIDTH-1:8],
| ^~~~~~~~~
%Error: //openlane/designs/RISCV_CPU/src/ct_lsu_st_dc.v:1384:56: Define or directive not defined: 'VA_WIDTH' : ... Suggested alternative: 'PA_WIDTH'
1384 | assign st_dc_bkpta_addr[VA_WIDTH-1:0] = {st_dc_va[VA_WIDTH-1:8],
| ^~~~~~~~~
%Error: //openlane/designs/RISCV_CPU/src/ct_lsu_st_dc.v:1388:25: Define or directive not defined: 'VA_WIDTH' : ... Suggested alternative: 'PA_WIDTH'
1388 | assign st_dc_bkptb_addr[VA_WIDTH-1:0] = {st_dc_va[VA_WIDTH-1:8],
| ^~~~~~~~~
%Error: //openlane/designs/RISCV_CPU/src/ct_lsu_st_dc.v:1388:56: Define or directive not defined: 'VA_WIDTH' : ... Suggested alternative: 'PA_WIDTH'
1388 | assign st_dc_bkptb_addr[VA_WIDTH-1:0] = {st_dc_va[VA_WIDTH-1:8],
| ^~~~~~~~~
%Error: //openlane/designs/RISCV_CPU/src/ct_lsu_st_dc.v:1393:61: Define or directive not defined: 'VA_WIDTH' : ... Suggested alternative: 'PA_WIDTH'
1393 | ^ (st_dc_had_bkpta_addr[VA_WIDTH-1:0] | ^~~~~~~~~ %Error: //openlane/designs/RISCV_CPU/src/ct_lsu_st_dc.v:1394:60: Define or directive not defined: 'VA_WIDTH'
: ... Suggested alternative: 'PA_WIDTH' 1394 | == st_dc_bkpta_addr[VA_WIDTH-1:0]);
| ^~~~~~~~~
%Error: //openlane/designs/RISCV_CPU/src/ct_lsu_st_dc.v:1397:61: Define or directive not defined: 'VA_WIDTH' : ... Suggested alternative: 'PA_WIDTH'
1397 | ^ (st_dc_had_bkptb_addr[VA_WIDTH-1:0] | ^~~~~~~~~ %Error: //openlane/designs/RISCV_CPU/src/ct_lsu_st_dc.v:1398:60: Define or directive not defined: 'VA_WIDTH'
: ... Suggested alternative: 'PA_WIDTH' 1398 | == st_dc_bkptb_addr[VA_WIDTH-1:0]);
| ^~~~~~~~~
%Error: //openlane/designs/RISCV_CPU/src/ct_l2cache_dirty_array_16way.v:33:29: Define or directive not defined: 'L2C_TAG_INDEX_WIDTH' 33 | parameter TAG_INDEX_WIDTH = L2C_TAG_INDEX_WIDTH;
| ^~~~~~~~~~~~~~~~~~~~
%Error: //openlane/designs/RISCV_CPU/src/ct_l2cache_dirty_array_16way.v:33:49: syntax error, unexpected ';', expecting TYPE-IDENTIFIER
33 | parameter TAG_INDEX_WIDTH = L2C_TAG_INDEX_WIDTH; | ^ %Error: //openlane/designs/RISCV_CPU/src/ct_l2cache_dirty_array_16way.v:76:3: syntax error, unexpected '.' 76 | .A (dirty_idx ), | ^ %Error: //openlane/designs/RISCV_CPU/src/openC910.v:1612:21: Define or directive not defined: 'PLIC_INT_NUM'
1612 | plic_top #(.INT_NUM(PLIC_INT_NUM+16), | ^~~~~~~~~~~~~ %Error: //openlane/designs/RISCV_CPU/src/openC910.v:1613:25: Define or directive not defined: 'PLIC_HART_NUM'
1613 | .HART_NUM(PLIC_HART_NUM), | ^~~~~~~~~~~~~~ %Error: //openlane/designs/RISCV_CPU/src/openC910.v:1614:23: Define or directive not defined: 'PLIC_ID_NUM'
1614 | .ID_NUM(PLIC_ID_NUM), | ^~~~~~~~~~~~ %Error: //openlane/designs/RISCV_CPU/src/openC910.v:1615:25: Define or directive not defined: 'PLIC_PRIO_BIT'
1615 | .PRIO_BIT(PLIC_PRIO_BIT), | ^~~~~~~~~~~~~~ %Error: //openlane/designs/RISCV_CPU/src/openC910.v:1616:29: Define or directive not defined: 'MAX_HART_NUM'
1616 | .MAX_HART_NUM(MAX_HART_NUM)) x_plic_top( | ^~~~~~~~~~~~~ %Error: //openlane/designs/RISCV_CPU/src/openC910.v:1651:21: Define or directive not defined: 'PLIC_INT_NUM'
1651 | assign plic_int_vld[PLIC_INT_NUM+15:0] = {pad_plic_int_vld[PLIC_INT_NUM-1:0],14'b0,l2c_plic_ecc_int_vld,1'b0};
| ^~~~~~~~~~~~~
%Error: //openlane/designs/RISCV_CPU/src/openC910.v:1651:61: Define or directive not defined: 'PLIC_INT_NUM' 1651 | assign plic_int_vld[PLIC_INT_NUM+15:0] = {pad_plic_int_vld[PLIC_INT_NUM-1:0],14'b0,l2c_plic_ecc_int_vld,1'b0}; | ^~~~~~~~~~~~~ %Error: //openlane/designs/RISCV_CPU/src/openC910.v:1652:21: Define or directive not defined: 'PLIC_INT_NUM'
1652 | assign plic_int_cfg[PLIC_INT_NUM+15:0] = {pad_plic_int_cfg[PLIC_INT_NUM-1:0],16'b0};
| ^~~~~~~~~~~~~
%Error: //openlane/designs/RISCV_CPU/src/openC910.v:1652:61: Define or directive not defined: 'PLIC_INT_NUM' 1652 | assign plic_int_cfg[PLIC_INT_NUM+15:0] = {pad_plic_int_cfg[PLIC_INT_NUM-1:0],16'b0}; | ^~~~~~~~~~~~~ %Error: //openlane/designs/RISCV_CPU/src/ct_ifu_icache_predecd_array0.v:120:3: syntax error, unexpected '.' 120 | .A (ifu_icache_index[WIDTH:3] ), | ^ %Error: //openlane/designs/RISCV_CPU/src/ct_ebiu_read_channel.v:511:19: Define or directive not defined: 'SAB_DEPTH'
511 | parameter DEPTH = SAB_DEPTH; | ^~~~~~~~~~ %Error: //openlane/designs/RISCV_CPU/src/ct_ebiu_read_channel.v:511:29: syntax error, unexpected ';', expecting TYPE-IDENTIFIER 511 | parameter DEPTH = SAB_DEPTH;
| ^
%Error: //openlane/designs/RISCV_CPU/src/ct_ciu_snb_sab.v:800:20: Define or directive not defined: 'SAB_DEPTH' 800 | parameter DEPTH = SAB_DEPTH;
| ^~~~~~~~~~
%Error: //openlane/designs/RISCV_CPU/src/ct_ciu_snb_sab.v:800:30: syntax error, unexpected ';', expecting TYPE-IDENTIFIER
800 | parameter DEPTH = SAB_DEPTH; | ^ %Error: //openlane/designs/RISCV_CPU/src/ct_ciu_snb_sab.v:801:20: Define or directive not defined: 'SAB_RDEPTH'
801 | parameter RDEPTH = SAB_RDEPTH; | ^~~~~~~~~~~ %Error: //openlane/designs/RISCV_CPU/src/ct_ciu_snb_sab.v:801:31: syntax error, unexpected ';', expecting TYPE-IDENTIFIER 801 | parameter RDEPTH = SAB_RDEPTH;
| ^
%Error: //openlane/designs/RISCV_CPU/src/ct_ciu_snb_sab.v:802:20: Define or directive not defined: 'SAB_WDEPTH' 802 | parameter WDEPTH = SAB_WDEPTH;
| ^~~~~~~~~~~
%Error: //openlane/designs/RISCV_CPU/src/ct_ciu_snb_sab.v:802:31: syntax error, unexpected ';', expecting TYPE-IDENTIFIER
802 | parameter WDEPTH = SAB_WDEPTH; | ^ %Error: //openlane/designs/RISCV_CPU/src/ct_ciu_snb_dp_sel.v:105:19: Define or directive not defined: 'SAB_DEPTH'
105 | parameter DEPTH = SAB_DEPTH; | ^~~~~~~~~~ %Error: //openlane/designs/RISCV_CPU/src/ct_ciu_snb_dp_sel.v:105:29: syntax error, unexpected ';', expecting TYPE-IDENTIFIER 105 | parameter DEPTH = SAB_DEPTH;
| ^
%Error: //openlane/designs/RISCV_CPU/src/ct_l2c_cmp.v:462:30: Define or directive not defined: 'L2C_TAG_INDEX_WIDTH' 462 | parameter TAG_INDEX_LENTH = L2C_TAG_INDEX_WIDTH;
| ^~~~~~~~~~~~~~~~~~~~
%Error: //openlane/designs/RISCV_CPU/src/ct_l2c_cmp.v:462:50: syntax error, unexpected ';', expecting TYPE-IDENTIFIER
462 | parameter TAG_INDEX_LENTH = L2C_TAG_INDEX_WIDTH; | ^ %Error: //openlane/designs/RISCV_CPU/src/ct_l2c_cmp.v:463:30: Define or directive not defined: 'L2C_TAG_DATA_WIDTH'
463 | parameter TAG_TAG_LENTH = L2C_TAG_DATA_WIDTH; | ^~~~~~~~~~~~~~~~~~~ %Error: //openlane/designs/RISCV_CPU/src/ct_l2c_cmp.v:463:49: syntax error, unexpected ';', expecting TYPE-IDENTIFIER 463 | parameter TAG_TAG_LENTH = L2C_TAG_DATA_WIDTH;
| ^
%Error: Exiting due to too many errors enco
verilator.log
untered; --error-limit=50

tried to convert the cpu_cfig.h and sysmap.h to .v by using `parameter still no help

The group does not exist or can not be searched.

Hi!

I was looking to get started with using T-Head-Semi's openc910 core, but just had a few questions about the setup required.

1. What are the minimum specifications (like the number of LUTs) an FPGA board must have to be able to run this core? Are there any recommended FPGAs?
2. Can this core run Linux? What other operating system(s) does this core support?
3. Lastly, is there any recommended OS which I should use when working with the files for this core?

It is Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension.
I am curious will it be released in the future?

For the provided toolchain URL, right now, is not posible to register and download, (AFAIK) from out of china phone number.
https://occ.t-head.cn/community/download?id=3948120165480468480

With an spanish phone number (+34XXXXXXXXX), I cannot register an account to download the toolchain.
I tried with my dingchat account, but again the form asked for a +86 phone number

Sadly the RiscV toolchain provided with Ubuntu does not support newlib-nano

/openc910/smart_run/work#  make -s clean && make -s all CPU_ARCH_FLAG_0=c910  ENDIAN_MODE=little-endian CASENAME=hello_world FILE=hello_world
riscv64-unknown-elf-gcc: fatal error: cannot read spec file 'nano.specs': No such file or directory

¿Must I build my own RiscV tool chain (with newlib-nano)?

Is the source code generated from some other source language? We notice the gen_RTL directory name.

This would be useful to know; for example, will pull requests to this repo be accepted, or would the fixes need to be made upstream and then the RTL regenerated by T Head?

/T-head-Semi/openc910/smart_run$ make
########## Smart Help Info ##########
This Makefile is the entrance of T-Head Smart simulation environment
Usage: make [target] [arguments]
Available targets:
compile : compile the RTL and Smart tbench (using vcs or ius)
showcase : list all valid cases under current configuration
buildcase CASE=[casename] : clean and compile the .c/.s case [casename]
[casename]_build : compile the .c/.s case [casename]
runcase CASE=[casename] : run the case [casename]
regress : run all cases and summarize the regress result
memlist : generate sram list with the help of VCS/Verdi
cleansim : clean files generated by simulator in ./work
cleancase : clean files generated by GNU in ./work
clean : clean ./work
Optional arguments:
SIM= : options: vcs / nc / verilator(use version 4.215 or newer)
CASE= : options: the list print by 'make showcase'
DUMP= : options: on / off
Examples:
make runcase CASE=dhry : run case 'dhry' (by iverilog withtout dump)
make runcase CASE=dhry SIM=nc : run case 'dhry' (by nc withtout dump)
make runcase CASE=dhry DUMP=on : run case 'dhry' with dump
/bin/sh: 1: Syntax error: Unterminated quoted string
Makefile:249: recipe for target 'help' failed
make: *** [help] Error 2

Looking in the instruction decoder I encountered non-standard RISC-V instructions.

Opcodes, of these non-standard Store instructions, seem to be decoded here:

This also applies to load-type instructions. And there is probably some other instructions that I haven't quite identified yet.

I am looking for documentation about this RISC-V extension, but I couldn't find anything.
Could you provide documentation about it?

从代码里面 最初应该有c模型的，但是好像注释掉了， 什么地方能够搞到有完整c模型代码的版本呢

reveal：
Warning-[STASKW_CO1] Cannot open file
The file 'data.pat' could not be opened. No such file or directory.
Please ensure that the file exists with proper permissions.

Warning-[STASKW_RMCOF] Cannot open file
../logical/tb/tb.v, 137
Cannot open file 'data.pat' passed as argument to $readmem.
Please verify that the first argument to $readmem is a file that exists with
proper permissions.

Could someone please tell me what the problem is, or how to fix it

Reporting errors whether SIM=verilator %Error: Cannot find file containing module: # or SIM=iverilog /home/v***r/codes/fun/openc910/newlib/bin/riscv64-unknown-elf-gcc: Command not found

Anyone meets the same problem? I v installed the toolchain "Xuantie-900-gcc-elf-newlib-mingw-V2.6.1-20220906" in my Makefile already.

I'm trying to sort out how to run this, it looks like there's some GCC arguments that aren't upstream. I found some links to binary toolchains, but I'd prefer to build my own toolchains from source. Is that source online anywhere?

could you provide address map for C910?