jian-fang Goto Github PK

100-days-of-ml-code

100 Days of ML Coding

100-days-of-ml-code-1

100-Days-Of-ML-Code中文版

a2-boot

a2i

a2o

a2o-1

The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue. It is now being updated for compliancy and integration into open projects.

a2p

a2p-mpw7

A2P Core with ToySRAM memories

ariane-wrapper

Wrapper for ETH Ariane Core

arrow

Apache Arrow is a cross-language development platform for in-memory data. It specifies a standardized language-independent columnar memory format for flat and hierarchical data, organized for efficient analytic operations on modern hardware. It also provides computational libraries and zero-copy streaming messaging and interprocess communication. Languages currently supported include C, C++, Java, JavaScript, Python, and Ruby.

axi2mem

capi-streaming-framework

AFU framework for streaming applications with CAPI.

capi-textswap

A "Hello World" for the Power8 CAPI Interface. Includes application C and RTL code.

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

chisel-tutorial

chisel tutorial exercises and answers

chiseltest

The official testing library for Chisel circuits.

core-v-docs

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

cores-swerv-eh2

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

dicells

Cell Library for Delay Insensitive Synchronous Hardware

digital-design-lab

e200_opensource

The Ultra-Low Power RISC Core

espresso-ab-1.0

espresso logic minimizer (https://embedded.eecs.berkeley.edu/pubs/downloads/espresso/index.htm)

feather

Feather: fast, interoperable binary data frame storage for Python, R, and more powered by Apache Arrow

force-riscv

Instruction Set Generator initially contributed by Futurewei

fpga_hash_join

fudian

Open source high performance IEEE-754 floating unit

gem5

hardware-zstd-compression-unit