♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
Home Page: https://github.com/stnolting/neorv32
License: BSD 3-Clause "New" or "Revised" License
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Hi,
I have just cloned the repo and installed the latest version of https://github.com/YosysHQ/oss-cad-suite-build (2022-09-25). I am able to run convert.sh correctly, but when I run iverilog_sim.sh I get the following error (trimmed as it is basically the same thing over and over):
$ ./iverilog_sim.sh
../src/neorv32_verilog_wrapper.v:20290: error: Could not find variable ``n1647_oport['sd1023]'' in ``neorv32_verilog_tb.uut.neorv32_top_inst.neorv32_boot_rom_inst_true_neorv32_boot_rom_inst''
../src/neorv32_verilog_wrapper.v:20291: error: Could not find variable ``n1647_oport['sd1022]'' in ``neorv32_verilog_tb.uut.neorv32_top_inst.neorv32_boot_rom_inst_true_neorv32_boot_rom_inst''
../src/neorv32_verilog_wrapper.v:20292: error: Could not find variable ``n1647_oport['sd1021]'' in ``neorv32_verilog_tb.uut.neorv32_top_inst.neorv32_boot_rom_inst_true_neorv32_boot_rom_inst''
../src/neorv32_verilog_wrapper.v:20293: error: Could not find variable ``n1647_oport['sd1020]'' in ``neorv32_verilog_tb.uut.neorv32_top_inst.neorv32_boot_rom_inst_true_neorv32_boot_rom_inst''
../src/neorv32_verilog_wrapper.v:20294: error: Could not find variable ``n1647_oport['sd1019]'' in ``neorv32_verilog_tb.uut.neorv32_top_inst.neorv32_boot_rom_inst_true_neorv32_boot_rom_inst''
...
../src/neorv32_verilog_wrapper.v:21303: error: Could not find variable ``n1647_oport['sd10]'' in ``neorv32_verilog_tb.uut.neorv32_top_inst.neorv32_boot_rom_inst_true_neorv32_boot_rom_inst''
../src/neorv32_verilog_wrapper.v:21304: error: Could not find variable ``n1647_oport['sd9]'' in ``neorv32_verilog_tb.uut.neorv32_top_inst.neorv32_boot_rom_inst_true_neorv32_boot_rom_inst''
../src/neorv32_verilog_wrapper.v:21305: error: Could not find variable ``n1647_oport['sd8]'' in ``neorv32_verilog_tb.uut.neorv32_top_inst.neorv32_boot_rom_inst_true_neorv32_boot_rom_inst''
../src/neorv32_verilog_wrapper.v:21306: error: Could not find variable ``n1647_oport['sd7]'' in ``neorv32_verilog_tb.uut.neorv32_top_inst.neorv32_boot_rom_inst_true_neorv32_boot_rom_inst''
../src/neorv32_verilog_wrapper.v:21307: error: Could not find variable ``n1647_oport['sd6]'' in ``neorv32_verilog_tb.uut.neorv32_top_inst.neorv32_boot_rom_inst_true_neorv32_boot_rom_inst''
../src/neorv32_verilog_wrapper.v:21308: error: Could not find variable ``n1647_oport['sd5]'' in ``neorv32_verilog_tb.uut.neorv32_top_inst.neorv32_boot_rom_inst_true_neorv32_boot_rom_inst''
../src/neorv32_verilog_wrapper.v:21309: error: Could not find variable ``n1647_oport['sd4]'' in ``neorv32_verilog_tb.uut.neorv32_top_inst.neorv32_boot_rom_inst_true_neorv32_boot_rom_inst''
../src/neorv32_verilog_wrapper.v:21310: error: Could not find variable ``n1647_oport['sd3]'' in ``neorv32_verilog_tb.uut.neorv32_top_inst.neorv32_boot_rom_inst_true_neorv32_boot_rom_inst''
../src/neorv32_verilog_wrapper.v:21311: error: Could not find variable ``n1647_oport['sd2]'' in ``neorv32_verilog_tb.uut.neorv32_top_inst.neorv32_boot_rom_inst_true_neorv32_boot_rom_inst''
../src/neorv32_verilog_wrapper.v:21312: error: Could not find variable ``n1647_oport['sd1]'' in ``neorv32_verilog_tb.uut.neorv32_top_inst.neorv32_boot_rom_inst_true_neorv32_boot_rom_inst''
../src/neorv32_verilog_wrapper.v:21313: error: Could not find variable ``n1647_oport['sd0]'' in ``neorv32_verilog_tb.uut.neorv32_top_inst.neorv32_boot_rom_inst_true_neorv32_boot_rom_inst''
1024 error(s) during elaboration.
./neorv32-verilog-sim: Unable to open input file.
Could you please help me understand what I am doing wrong? I also tried to run the check.sh script from the github CI but it gives the same output.
Some other details:
uname -a:
Linux emu 5.15.0-48-generic #54~20.04.1-Ubuntu SMP Thu Sep 1 16:17:26 UTC 2022 x86_64 x86_64 x86_64 GNU/Linux
iverilog -v:
Icarus Verilog version 12.0 (devel) (s20150603-1609-gfd69d4e09)
...
ghdl -v:
GHDL 2.0.0-dev (tarball) [Dunoon edition] open-tool-forge.nightly-20210921
Compiled with GNAT Version: 9.3.0
mcode code generator
...
In the wrapper file for the example processor config the FAST_SHIFT_EN is set true while the CPU_EXTENSION_RISCV_B is not existent in this file. Is this just a "typo" or what is the reasoning behind it? If there is any I would like to understand that.
Is it the idea hey the fast barrel shifter dedicated hardware unit is used also in the execution of other instructions that the ones contained in the RISCV_B extension?
Hi, just wanted to ask how can I convert the core vhd files and the memory vhd files into verilog separately ?
hi. is the verilog version 100% same as vhdl version?
thanks
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