this webpage shows the following line

git clone https://github.com/softwareradiosystems/zynq_timestamping.git --recursive

I think it should use https://github.com/srsran/zynq_timestamping.git

Add a register in the FPGA so that the software can validate that the correct bitstream is loaded when initializing the RF.

The following occurs during initialization of the AntSDR. I'm curious if the failed to create X is an issue. I've yet to establish a connection between the AntSDR and B205mini even after creating a direct connection between the two with appropriate cables and attenuators.

sudo LD_LIBRARY_PATH=./bin_app nice -20 ./bin_app/srsue/srsue ./bin_app/srsue/ue.conf --gw.netns=ue1
Reading configuration file ./bin_app/srsue/ue.conf...

Built in Release mode using commit 254cc719a on branch HEAD.

Opening 1 channels in RF device=iio with args=n_prb=6,context=ip:192.168.1.10
Active RF plugins: libsrsran_rf_iio.so
Inactive RF plugins:
Supported RF device list: iio
CH0 n_prb=6
CH0 context=ip:192.168.1.10
failed to create the rf_port with A_BALENCED
failed to create the rf_port with A
Waiting PHY to initialize ... done!
Attaching UE...
Setting manual TX/RX offset to 82 samples

I make it down to 5/5 attempts instead.

Found Cell:  Mode=FDD, PCI=1, PRB=6, Ports=1, CP=Normal, CFO=3.7 KHz
Setting manual TX/RX offset to 82 samples
Found PLMN:  Id=00101, TAC=7
Random Access Transmission: seq=19, tti=2261, ra-rnti=0x2
Random Access Transmission: seq=4, tti=2281, ra-rnti=0x2
Random Access Transmission: seq=47, tti=2301, ra-rnti=0x2
Random Access Transmission: seq=37, tti=2321, ra-rnti=0x2
Random Access Transmission: seq=51, tti=2341, ra-rnti=0x2
Random Access Transmission: seq=42, tti=2361, ra-rnti=0x2
Random Access Transmission: seq=9, tti=2381, ra-rnti=0x2
Random Access Transmission: seq=20, tti=2401, ra-rnti=0x2
Random Access Transmission: seq=10, tti=2421, ra-rnti=0x2
Random Access Transmission: seq=36, tti=2441, ra-rnti=0x2
Attach failed (attempt 5/5)

Hello,

Projects build documentation mentions the following:

Prerequisites: 

SRS Python tools:

cd python_tools
sudo pip3 install .

However, this command is failing as pip3 is unable to find "setup.py" file.

Please add setup.py to fix this issue.

Regards.

I think the submodules are missing

benja@:/mnt/d/git/zynq_timestamping/app$ ./prepare.sh
--> Current UE configuration
• Board IP: 10.12.1.201
• freq_offset: -4100
• rx_gain: 50
• time_adv_nsamples: 82

cp: cannot create regular file 'srsRAN/lib/examples/usrp_txrx.c': No such file or directory
./prepare.sh: line 33: cd: srsRAN: No such file or directory

See if the ZCU App Note needs to be modified to cover any missing dependency (e.g., FFTW) and, in that case, detail how to install (e.g., through the petalinux config menu, by adding a custom recipe).

I am trying running srsenb with the timestamping driver, setting in enb.conf:
n_prb = 6
device_name = iio
device_args = context=usb:

Also changed prach_freq_offset to zero in sib.conf to compatibilize with n_prb=6

I see no power coming out from the TX channel at the announced DL frequency.

If I run the txrx_test, I can sense with a spectrum analyzer that the TX antenna is transmitting at the announced freq,
but I sense nothing when running the srsenb.

(also on some runs, although not all runs, I get the "Error reading rx ringbuffer. Invalid header" as in the
issue #35 )

While creating a timestamping project for zcu102, the process successfully builds the ad9361 libraries but fails to complete the with srs-fpga-tools command not found error. The python version and all its dependencies are provided as per requirement.

hyeboy@hyeboy:~/Pictures/zynq_timestamping/projects/zcu102$ ./create_project.sh project
###################################################################

• Mode: project
  ###################################################################
  Building axi_ad9361 library [/home/hyeboy/Pictures/zynq_timestamping/projects/zcu102/hdl/library/axi_ad9361/axi_ad9361_ip.log] ... OK
  Building util_cdc library [/home/hyeboy/Pictures/zynq_timestamping/projects/zcu102/hdl/library/util_cdc/util_cdc_ip.log] ... OK
  Building util_axis_fifo library [/home/hyeboy/Pictures/zynq_timestamping/projects/zcu102/hdl/library/util_axis_fifo/util_axis_fifo_ip.log] ... OK
  Building axi_dmac library [/home/hyeboy/Pictures/zynq_timestamping/projects/zcu102/hdl/library/axi_dmac/axi_dmac_ip.log] ... OK
  Building util_cpack2 library [/home/hyeboy/Pictures/zynq_timestamping/projects/zcu102/hdl/library/util_pack/util_cpack2/util_cpack2_ip.log] ... OK
  Building util_upack2 library [/home/hyeboy/Pictures/zynq_timestamping/projects/zcu102/hdl/library/util_pack/util_upack2/util_upack2_ip.log] ... OK
  Building util_wfifo library [/home/hyeboy/Pictures/zynq_timestamping/projects/zcu102/hdl/library/util_wfifo/util_wfifo_ip.log] ... OK
  Building util_rfifo library [/home/hyeboy/Pictures/zynq_timestamping/projects/zcu102/hdl/library/util_rfifo/util_rfifo_ip.log] ... OK
  Building util_tdd_sync library [/home/hyeboy/Pictures/zynq_timestamping/projects/zcu102/hdl/library/util_tdd_sync/util_tdd_sync_ip.log] ... OK
  Building axi_sysid library [/home/hyeboy/Pictures/zynq_timestamping/projects/zcu102/hdl/library/axi_sysid/axi_sysid_ip.log] ... OK
  Building sysid_rom library [/home/hyeboy/Pictures/zynq_timestamping/projects/zcu102/hdl/library/sysid_rom/sysid_rom_ip.log] ... OK
  Building util_clkdiv library [/home/hyeboy/Pictures/zynq_timestamping/projects/zcu102/hdl/library/xilinx/util_clkdiv/util_clkdiv_ip.log] ... OK
  ./create_project.sh: line 44: srs-tools-fpga-vivado-ip-pack: command not found
  "!!" command failed with exit code 127.

I am facing an error after running default run_txrx_test_plutosdr.sh as shown below.

the left side is the output of plutosdr dmesg.

do I need to update srs with metadata libiio driver inside pluto, I have not seen any info about it, Thanks

I am trying to implement the zynq_timestamping solution by porting the existing implementation into ZC702/ZC706 + FMCOMMS5.
Having as reference the Block design of the ZCU102 and AntSDR, I managed to port the the solution into my hardware.
So far, I managed to make it work with the txrx and pdsch_enodeb/ue examples.

Although, when I tried to run the srsenb, I realized that the SDR didn't transmit any samples. I added some ILA debug cores on the FPGA to see what going on, and I saw that the timestamp of the TX packets where late with respect of the current sample counter and thus the packets were discarded.

My setup is a Host PC (i9 CPU, 32GB RAM) that runs the SRSRAN applications that exchange samples with the ZC702/ZC706 through Gigabit Ethernet using LibIIO.

From this code line I understand that the time between each RX and TX must be 4ms. So the latency of my setup (ADC timestamp insertion -> receive RX packet on srsenb -> add 4ms on the timestamp and create TX packet -> DAC timestamp control) is greater than 4ms.

The example pdsch_enodeb doesn't use timestamping that is why there is no late situation. On the other hand, the txrx example also has this 4ms interval between RX - TX, but it seems that the packets doesn't arrive late on the DAC_timestamping.

I tried to set in performance mode both Host PC and Zynq's ARM but still no success of running srsenb. Also tried different memory sizes on DAC_timestamping as well as different n_prbs (6 and 15) and ringbuffer sizes of the IIO plugin.

Is there anything else that am I missing or my setup isn't enough to run srsRAN? I appreciate any help.

I tried to build the ADALM-PLUTO project with Ubuntu 20.04. I used python3.10 to build the python tools. However, when I typed "/create_project.sh bitstream", the project was stuck with axi_ad9361 and I used Ctrl-C to exit the building process.

haohwa@chaohwa-ThinkPad-Edge-E540:~/zynq_timestamping/projects/pluto$ ./create_project.sh bitstream
###################################################################

• Mode: bitstream
  ###################################################################
  Building axi_ad9361 library [/home/chaohwa/zynq_timestamping/projects/pluto/hdl/library/axi_ad9361/axi_ad9361_ip.log] ...^Cmake[1]: *** [../scripts/library.mk:71: component.xml] Interrupt
  make: *** [Makefile:55: gen-adi-ips] Interrupt

In my Ubuntu 20.04, the cmake version is 3.16.3. The gcc version is 9.4.0.

However, I don't have any problem building the project in Ubuntu 18.04. So how should I fix it in Ubuntu 20,04?

I have already installed the fpga bitstream to a pluto adalm v0.34, and compiled the srsenb, and set cpu scaling to performance. But when starting srsenb I get an error when trying to create the TX buffer:

$ srsenb
Active RF plugins: libsrsran_rf_uhd.so libsrsran_rf_blade.so libsrsran_rf_iio.so
Inactive RF plugins:
--- Software Radio Systems LTE eNodeB ---
Reading configuration file /etc/srsran/enb.conf /etc/srsran/sib.conf /etc/srsran/rr.conf /etc/srsran/rb.conf
Built in Release mode using commit 254cc719a on branch HEAD.
Opening 1 channels in RF device=iio with args=context=usb:
Supported RF device list: UHD bladeRF iio file
CH0 context=usb:
app/srsRAN/lib/src/phy/rf/rf_iio_imp.c:542: Could not create TX buffer (pretended size:1928) errno=2
==== eNodeB started ===
Type to view trace
Setting frequency: DL=2680.0 Mhz, UL=2560.0 MHz for cc_idx=0 nof_prb=6

Any clues for this error in the iio_device_create_buffer(...) function?

Looking to test this out on the AntSDR E310 per the application note. I noticed there's a BIN file pre-built. I think the bottom of this page is what I'd aim to use, but with a path which reflects the correct location of the downloaded BIN file.

https://srsran.github.io/zynq_timestamping/bitstream/antsdr_project.html#antsdr-project

Is that correct? Also, is it best to have the most recent image on the AntSDR github page loaded onto the internal SD Card?

Current "Make gen-boot-load" fails. Probably there is a problem in the order of the commands. If I run them individually in pluto, after uploading the bitstream to /lib/firmware I get:

$ cd /lib/firmware/; echo system_top.bit.bin > /sys/class/fpga_manager/fpga0/firmware
$ echo 79024000.cf-ad9361-dds-core-lpc > /sys/bus/platform/drivers/cf_axi_dds/unbind
$ echo 79020000.cf-ad9361-lpc > /sys/bus/platform/drivers/cf_axi_adc/unbind
$ echo 7c400000.dma > /sys/bus/platform/drivers/dma-axi-dmac/unbind
$ echo 7c420000.dma > /sys/bus/platform/drivers/dma-axi-dmac/unbind
$ echo 7c420000.dma > /sys/bus/platform/drivers/dma-axi-dmac/bind
$ echo 7c400000.dma > /sys/bus/platform/drivers/dma-axi-dmac/bind
$ echo 79024000.cf-ad9361-dds-core-lpc > /sys/bus/platform/drivers/cf_axi_dds/bind
$ echo 79020000.cf-ad9361-lpc > /sys/bus/platform/drivers/cf_axi_adc/bind
sh: write error: No such device

$ iio_info -a local | egrep iio:device
Using auto-detected IIO context at URI "local:"
iio:device0: ad9361-phy
iio:device1: xadc
iio:device2: cf-ad9361-dds-core-lpc (buffer capable)

It can be seen that device iio:device3: cf-ad9361-lpc (buffer capable) is missing at this point, so the echo command fails.

Any clues how to reorder commands to fix it?

# cd /lib/firmware; echo system_top.bit.bin > /sys/class/fpga_manager/fpga0/firmware
# echo 79024000.cf-ad9361-dds-core-lpc > /sys/bus/platform/drivers/cf_axi_dds/unbind
# echo 79020000.cf-ad9361-lpc > /sys/bus/platform/drivers/cf_axi_adc/unbind
# echo 7c400000.dma > /sys/bus/platform/drivers/dma-axi-dmac/unbind
# echo 7c420000.dma > /sys/bus/platform/drivers/dma-axi-dmac/unbind
# echo 7c420000.dma > /sys/bus/platform/drivers/dma-axi-dmac/bind
# echo 7c400000.dma > /sys/bus/platform/drivers/dma-axi-dmac/bind
# echo 79024000.cf-ad9361-dds-core-lpc > /sys/bus/platform/drivers/cf_axi_dds/bind
# echo 79020000.cf-ad9361-lpc > /sys/bus/platform/drivers/cf_axi_adc/bind
sh: write error: No such device

this only happens with the new system_top.bit.bin and the same thing happens when compiling or using the release build. unbinding and rebinding without the new FPGA firmware works fine.

Currently the FPGA flags late/underflow situations, but those are not forwarded to the CPU and, thus, no reporting is provided. The FPGA flags should be forwarded to the driver so as to print warnings to make the user aware of the communication bottleneck.

Setup:
22.04 Ubuntu (DragonOS) running on a Valve Steam Deck. Libiio and other analog requirements were from repo, libiio23, however I also tried 24. Firmware on the AntSDR was the latest available as of yesterday on the AntSDR GitHub page, BIN was replaced with timestamping pre-built file. The AntSDR was within about a foot of a b205mini in a contained space, everything was run on the Steam Deck itself.

Expectation:
AntSDR connects as a UE to the b205mini.

Result:
AntSDR had what seems to be no issue starting up with the exception of Failed to create the rf_port with A_BALENCED and A. However, after finding the cell it would go between line after line of . or something along the lines of the following

Setting manual TX/RX offset to 82 samples
ERROR: READ ALL: -9
ERROR: READ INTEGER: -9

and then eventually spamming all red with the following
/home/dragon/zynq_timestamping/sw/lib/src/phy/rf/rf_iio_imp.c:796: Error refilling buf -9

After which I would ctrl-c and start it all over. I could do this maybe 3-4 times or so before the AntSDR became unresponsive and I would have to reboot it and try again. No connection has been made between the AntSDR and b205mini (yet). I plan to move on to running everything on my laptop next.

Add the testbench and related python scripts to enable a basic functional simulation of the zynq timestamping solution

Hi! We have compiled last version (jan 11-2023) and generated the bitstream and installed it on AndtSDR E310v1.
We can execute srsenb with device_name=iio and connect to the E310 via giga-ethernet, configured for 6 PRB's.

The reader thread (which fills the ringbuffer buckets) is getting the timestamps from the FPGA, although it does not seem to get very stable timestamps, as the difference between them oscilates in the range <28000000,46000000>.

The processing thread is reading from the ring buffer, and finds the magic byte on the ringbuffer headers, although after about 4000 reads, it gets an invalid header error a few times, and then it continues reading but not checking the ringbuffer headers anymore.

Even though we do detect the downlink signal with a spectrum analyzer, the phone cannot see the nodeB.

Are the FPGA generated timestamps having the expected behaviour? Could the erratic FPGA timestamp values cause the inability to be detected by the cellular phone?

currently the prepare.sh scripts uses -j4, which makes it a bit slow on most modern systems. I would suggest to use -j$(nproc) instead

Hi,
I am testing the given app on the zynq7020 platform, and getting below logs and output plot. can anyone confirm my results are correct. It was stated in the documentation, the app will transmit the tomes at distinct 4msec. Please confirm.. Thanks

Opening RF device...
Active RF plugins: libsrsran_rf_iio.so
Inactive RF plugins:
Supported RF device list: iio
Trying to open RF device 'iio'
CH0 n_prb=6
CH0 context=ip:10.42.0.133
RF device 'iio' successfully opened
Subframe len: 1920 samples
Time advance: 0.000000 us
Set TX/RX rate: 1.92 MHz
Set RX gain: 15.0 dB
Set TX gain: 40.0 dB
Set TX/RX freq: 2400.00 MHz
Set TONE : TransmittionRx subframe 0
Transmitting Signal
Rx subframe 1
Rx subframe 2
Rx subframe 3
Transmitting Signal
Rx subframe 4
Rx subframe 5
Rx subframe 6
Rx subframe 7
Rx subframe 8
Transmitting Signal
Rx subframe 9
Rx subframe 10
Rx subframe 11
Rx subframe 12
Rx subframe 13
Rx subframe 14
Rx subframe 15
Rx subframe 16
Rx subframe 17
Rx subframe 18
Rx subframe 19
Done

In documentation the app note for zcu111 the croos compile section uses a wrong command

https://srsran.github.io/zynq_timestamping/app/zcu.html#cross-compiling-the-zynq-timestamping-library-and-tx-rx-example-application

instead of

./prepare.sh rfsoc

should be

./prepare.sh zcu111