irregular timestamp interval about zynq_timestamping HOT 1 OPEN

Hi @uptools,
The FPGA is indeed having a deterministic behavior and, thus, no timestamps will be skipped. If you see erratic numbering on the CPU side, you can pin it on a lack of performance. That is, samples are being lost due to the incapacity of the CPU to read all of them during the available time budget. I'd suggest playing with the buffer/packet sizes of the timestamping solution to adjust this time window (e.g., maybe using packets that contain 0.5 ms worth of data works better than trying to read 1 ms each time). Other than this, just make sure to compile in release mode, to give maximum priority to the srsenb process and to adjust the networking parameters affecting the E310 (again buffer sizes, etc.).

from zynq_timestamping.