This framework enables emulation of existing and emerging memories on FPGA boards. A soft core parameterizable and FPGA synthesizable memory prototype is provided. The memory model implements the memory components and accurately models their function and behavior.

The SystemVerilog model is located in the SysVerilog_Model directory. The SystemVerilog files implement the memory components and model their behavior, such as state and timing. The model is synthesizable and can be thought of as a memory soft core. The testbnch_* and wtestbnch_* files implement test benches and preformatted waveform configurations allowing for easy testing.

Bank-CPU Vivado Project and also Xilinx SDK Zynq Software Projects. Zynq CPU issues commands to Bank Hardware Module. Both Bank Hardware Module and Bank Software Module tested with same benchmark. Timing result are reported.

HLS project for DRAM Bank.

Software Project of DRAM Rank, where DRAM Rank is modeled in Software and tested in Software.

Reference Literature and also information on DDR3 / Command Timing

At this stage the files can be simulated in Vivado or ModelSim, synthesized (out of context). The development for integration into a full system is in progress.

Pull requests are welcome. For major changes, please open an issue first to discuss what you would like to change.

Please make sure to update tests as appropriate.

Please see the license file