Sergiu Mosanu's Projects
CNN MNIST
VIVADO HLS Training AXI Stream interface
David Canright's tiny AES S-boxes
Digital Design with Chisel
Generator Bootcamp Material: Learn Chisel the Right Way
getting started with Chisel
32-bit 5 stage RISC-V processor implementation in VHDL
Problem 2.3-7 from "Introduction to Algorithms" book by Cormen
CyanogenMod pleasant ringtone Twirl Away in high quality mp3 and wav
This code implements a switch for interconnecting 50 FPGA boards in a topology based on the Hoffman–Singleton graph
🚀✨ Help beginners to contribute to open source projects
General coding exercises in preparation for technical interviews
basic chisel3 lfsr
Linux on LiteX-VexRiscv
Small footprint and configurable DRAM core
Build your hardware, easily!
LiteX boards files
Memory Emulation on FPGA Boards
A Python toolbox for building complex digital hardware
Processing in Memory Emulation
Parallel Programming for FPGAs -- An open-source high-level synthesis book
A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the IEEE CAL 2015 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf
Config files for my GitHub profile.
This is an Object Oriented implementation of a Trie in python. The class contains setter and getter methods, and implements several useful functionalities. In addition, the class can generate graphviz dot code, which can be used to visualize the Trie.
U-Net Brain Tumor Segmentation in TensorFlow
Cheat sheet for Verilog
Zynq AXI4 Full Verilog Peripheral